System and method for modification of substrates

Patent metadata

Field	Value
Publication number	US-12424498-B2
Application number	US-201917413523-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Dec 13, 2018
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

Various embodiments of the present technology generally relate to substrate planarization. More specifically, some embodiments of the present technology relate a versatile systems and methods for precision surface topography optimization known as planarization on nominally planar substrates. In some embodiments, a method for planarization of a patterned substrate using inkjets can determine the global and nanoscale topography and pattern information of the patterned substrate. Based upon the global and nanoscale topography and pattern information, a drop pattern can be determined and then dispensed on the patterned substrate. A gap between the patterned substrate and a superstrate causing the dispensed drops can be closed to form a substantially contiguous film. The substantially contiguous film can be cured and the superstrate can be separated from the patterned substrate with substantially contiguous film on the patterned substrate.

First claim

What is claimed is:

1. A method for planarization of a patterned substrate using inkjets, the method comprising:
determining global and nanoscale topography and pattern information of the patterned substrate;
determining, based upon the global and nanoscale topography and the pattern information, a drop pattern;
dispensing the drop pattern on the patterned substrate;
closing a gap between the patterned substrate and a superstrate causing the dispensed drops to form a substantially contiguous film, wherein a thickness of the superstrate is designed to be spatially varying;
curing the substantially contiguous film; and
separating the superstrate and the patterned substrate from the substantially contiguous film on the patterned substrate.

2. The method of claim 1 , wherein the drop pattern is determined from a model of a process, an optimization scheme, and experimental data.

3. The method of claim 1 , further comprising loading a digital file encoded with data representing the global and nanoscale topography and the pattern information of the patterned substrate.

4. The method of claim 1 , wherein the drop pattern is computed using model-based optimization with inputs including the global and nanoscale topography and the pattern information, superstrate geometry, superstrate material properties, planarizing material properties, inkjet drop resolution, inkjet nozzle pitch, and tolerance information.

5. The method of claim 1 , wherein a surface of the superstrate is substantially more convex than the surface of the substrate at a location of a spreading front.

6. The method of claim 1 , wherein the superstrate has a sacrificial film and the method further comprises, ablating the sacrificial film to initiate peeling to separate the superstrate from the substrate.

7. The method of claim 1 , further comprising prioritizing planarization performance in a sub-region of a semiconductor device die.

8. The method of claim 7 , wherein the sub-region of the semiconductor device die corresponds to a portion of the semiconductor device die where a highest lithographic resolution is needed during a subsequent lithography process.

9. The method of claim 7 , wherein the sub-region is aligned orthogonal to a scanning direction of a photolithography scanner during exposure, wherein the photolithography scanner is a downstream process whose focus benefits from a surface topography control.

10. The method of claim 7 , wherein the inkjet is aligned parallel to the sub-region.

11. The method of claim 1 , wherein the gap is closed at a first station and curing is performed at a second station.

12. The method of claim 11 , wherein curing is performed at the end of a desired process time, where the desired process time is chosen to be high enough such that bubbles are substantially mitigated and low enough to prevent undesirable parasitics from affecting planarization performance.

Assignees

• Univ Texas

Inventors

• Sreenivasan Sidlgata V
• Singhal Shrawan
• Dunn Lawrence R

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G05B13/042

  in which a parameter or coefficient is automatically adjusted to optimise the performance · CPC title

• G03F7/16

  Coating processes; Apparatus therefor (applying coatings to base materials in general B05; applying photosensitive compositions to base for photographic purposes G03C1/74) · CPC title

• G03F7/0002 Primary

  Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping · CPC title