Light emitting diode display with redundancy scheme

US9865832B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9865832-B2
Application numberUS-201514798298-A
CountryUS
Kind codeB2
Filing dateJul 13, 2015
Priority dateMar 15, 2013
Publication dateJan 9, 2018
Grant dateJan 9, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LED devices. In one embodiment a redundant pair of micro LED devices are bonded to the array of bottom electrodes. In one embodiment, the array of micro LED devices are imaged to detect irregularities.

First claim

Opening claim text (preview).

What is claimed is: 1. A display panel with redundancy scheme comprising: a display substrate including a pixel area that includes an array of subpixels; an array of redundant micro LED device pairs within the array of subpixels, wherein each subpixel includes a redundant micro LED device pair, and each redundant micro LED device pair within a respective subpixel is designed to emit a same primary color emission; and one or more top electrode layers in electrical contact with the array of redundant micro LED device pairs; one or more micro LED device irregularities comprising one or more missing micro LED devices from one or more of the redundant micro LED device pairs of the array of redundant micro LED device pairs within the array of subpixels; and wherein the array of subpixels includes a first subpixel array, a second subpixel array, and a third subpixel array, wherein the first, second, and third subpixel arrays are designed to emit different primary color emissions. 2. The display panel of claim 1 , wherein the first subpixel array is designed to emit a red primary color emission, the second subpixel array is designed to emit a green primary color emission, and the third array subpixel array is designed to emit a blue primary color emission. 3. The display panel of claim 1 , wherein each micro LED device has a maximum width of 1 to 100 μm. 4. The display panel of claim 3 , wherein each micro LED device comprises a semiconductor material. 5. The display panel of claim 4 , wherein each micro LED device includes a p-doped layer, an n-doped layer, and a quantum well layer between the p-doped layer and the n-doped layer. 6. The display panel of claim 1 , further comprising circuitry to switch and drive the array of subpixels. 7. The display panel of claim 6 , wherein each micro LED device comprises a top conductive contact, a bottom conductive contact, and a bottom bonding layer that is diffused with a corresponding separate bonding layer on the display substrate, and the one or more top electrode layers is in electrical contact with the top conductive contacts of the array of redundant micro LED device pairs. 8. The display panel of claim 7 , further comprising a passivation layer material covering one or more bonding sites that correspond to the one or more missing micro LED devices, wherein the passivation layer material does not cover the top conductive contacts of the redundant micro LED device pairs. 9. The display panel of claim 7 , further comprising one or more cuts in the one or more top electrode layers over one or more bonding sites that correspond to the one or more missing micro LED devices. 10. The display panel of claim 1 , wherein the one or more top electrode layers is a single top electrode layer in electrical contact with the array of redundant micro LED device pairs. 11. The display panel of claim 10 , wherein the single top electrode layer is in electrical contact with a plurality of ground tie lines running between the array of subpixels through a plurality of openings formed in a planarization layer. 12. A display panel with redundancy scheme comprising: a display substrate including a pixel area that includes an array of subpixels; an array of redundant micro LED device pairs within the array of subpixels, wherein each subpixel includes a redundant micro LED device pair, and each redundant micro LED device pair within a respective subpixel is designed to emit a same primary color emission; and one or more top electrode layers in electrical contact with the array of redundant micro LED device pairs; wherein the array of subpixels includes a first subpixel array, a second subpixel array, and a third subpixel array, wherein the first, second, and third subpixel arrays are designed to emit different primary color emissions; circuitry to switch and drive the array of subpixels; and one or more micro LED device irregularities within the array of redundant micro LED device pairs, the irregularities selected from the group consisting of a missing micro LED device, a defective micro LED device, and a contaminated micro LED device; wherein each subpixel includes a first landing area and a second landing area, and a first micro LED device of a respective redundant micro LED device pair is bonded to the first landing area and a second micro LED device of the respective redundant micro LED device pair is bonded to the second landing area. 13. The display panel of claim 12 , wherein the first landing area is electrically disconnected from the circuitry. 14. The display panel of claim 13 , wherein the first landing area is cut to electrically disconnect the first landing area from the circuitry. 15. The display panel of claim 12 , wherein the circuitry is contained within an array of micro controller chips. 16. The display panel of claim 15 , wherein the array of micro controller chips is bonded to the display substrate. 17. The display panel of claim 16 , wherein each micro controller chip is bonded to the display substrate within the pixel area. 18. The display panel of claim 17 , wherein each micro controller chip is connected to a scan driver circuit and a data driver circuit. 19. The display panel of claim 12 , wherein the working circuitry is contained the display substrate.

Assignees

Inventors

Classifications

  • batch processes · CPC title

  • Means for moving chips, wafers or other parts, e.g. conveyor belts · CPC title

  • Means for applying energy, e.g. ovens or lasers · CPC title

  • Soldering or alloying · CPC title

  • Compression bonding, e.g. thermocompression bonding · CPC title

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What does patent US9865832B2 cover?
A display panel and method of manufacture are described. In an embodiment, a display substrate includes a pixel area and a non-pixel area. An array of subpixels and corresponding array of bottom electrodes are in the pixel area. An array of micro LED devices are bonded to the array of bottom electrodes. One or more top electrode layers are formed in electrical contact with the array of micro LE…
Who is the assignee on this patent?
Apple Inc
What technology area does this patent fall under?
Primary CPC classification G09G3/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jan 09 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).