Fin field-effect transistor semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-12424443-B2
Application number	US-202117545209-A
Country	US
Kind code	B2
Filing date	Dec 8, 2021
Priority date	Dec 8, 2021
Publication date	Sep 23, 2025
Grant date	Sep 23, 2025

Abstract

A fin field-effect transistor (“FinFET”) semiconductor device and method of forming the same. In one example, a semiconductor fin is formed over a semiconductor substrate. A conformal dielectric layer is formed on a top and side surfaces of the fin. A doped semiconductor layer is formed over the conformal dielectric layer, the doped semiconductor layer including a dopant. The doped semiconductor layer is heated thereby driving the dopant through the conformal dielectric layer and forming a doped region of the fin.

First claim

What is claimed:

1. A method of forming an integrated circuit, comprising:
forming a semiconductor fin over a semiconductor substrate;
forming a conformal dielectric layer on a top and side surfaces of the fin;
forming a doped semiconductor layer over the conformal dielectric layer, the doped semiconductor layer including a dopant;
heating the doped semiconductor layer thereby driving the dopant through the conformal dielectric layer thereby forming a doped region of the fin; and
forming an undoped semiconductor layer over the doped semiconductor layer and then annealing the doped and undoped semiconductor layers.

2. The method as recited in claim 1 , wherein the conformal dielectric layer is a thermal oxide layer.

3. The method as recited in claim 1 , wherein the doped semiconductor layer includes polysilicon.

4. The method as recited in claim 1 , wherein the dopant includes boron.

5. The method as recited in claim 1 , wherein the conformal dielectric layer has a thickness of about 3.0 nm.

6. The method as recited in claim 1 , wherein the doped semiconductor layer has a thickness of about 40 nm.

7. The method as recited in claim 1 , wherein the doped and undoped semiconductor layers are formed in a furnace, and further comprising performing an air break between the forming the doped semiconductor layer and the undoped semiconductor layer.

8. The method as recited in claim 1 , wherein the doped semiconductor layer has an as-formed dopant concentration of about 1e18 cm −3 .

9. The method as recited in claim 1 , wherein the doped region is a drift region of a metal-oxide semiconductor (MOS) Fin field-effect transistor (FinFET).

10. A method of forming a semiconductor device, comprising:
forming a fin above a substrate;
forming a thermal oxide layer over a top surface and sidewalls of the fin;
forming a doped layer over the thermal oxide layer, the thermal oxide layer being configured to control a dopant diffusion of the doped layer into the fin; and
forming an undoped polysilicon layer over the doped layer,
wherein a dopant in the doped layer is diffused into the fin through the thermal oxide layer by a thermal annealing process at 900° C. to 1200° C. for 20 to 50 minutes.

11. The method as recited in claim 10 wherein the undoped polysilicon layer has a thickness in a range of 150 nm to 300 nm.

12. The method as recited in claim 10 wherein the thermal oxide layer is in a range of 2.0 to 5.0 nm.

13. The method as recited in claim 10 wherein the doped layer is in a range of 20 nm to 100 nm.

14. The method as recited in claim 10 wherein the doped layer comprises at least one of boron, phosphorus and arsenic.

15. The method as recited in claim 10 further comprising forming the thermal oxide layer at a bottom of a trench proximate the fin and forming the doped layer thereover.

16. The method as recited in claim 10 wherein a doping density of the doped layer at the top surface as compared to the sidewalls is within 20 percent.

17. A method of forming a semiconductor device, comprising:
forming a fin above a substrate;
forming a thermal oxide layer over a top surface and sidewalls of the fin;
forming a doped layer over the thermal oxide layer, the thermal oxide layer being configured to control a dopant diffusion of the doped layer into the fin; and
forming an undoped polysilicon layer over the doped layer,
wherein a doping density of the doped layer at the top surface as compared to the sidewalls is within 20 percent.

Assignees

• Texas Instruments Inc

Inventors

• Srinivasan Bhaskar
• Idol Walter Scott
• Chuang Ming-Yeh
• Goodlin Brian

Classifications

• H10P32/171

  being group IV material · CPC title

• H10P32/14 Primary

  within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase · CPC title

• H10P32/1412

  through the applied layer · CPC title

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title

• H10D30/024 Primary

  of fin field-effect transistors [FinFET] · CPC title