In-situ doped polysilicon filler for trenches

Patent metadata

Field	Value
Publication number	US-9691751-B2
Application number	US-201414570530-A
Country	US
Kind code	B2
Filing date	Dec 15, 2014
Priority date	Dec 15, 2014
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A method of fabricating an integrated circuit (IC) includes etching a trench in a semiconductor substrate having an aspect ratio (AR) ≧5 and a trench depth ≧10 μm. A dielectric liner is formed along the walls of the trench to form a dielectric lined trench. In-situ doped polysilicon is deposited into the trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler therein. The doped polysilicon filler after completion of fabricating the IC is essentially polysilicon void-free and has a 25° C. sheet resistance ≦100 ohms/sq. The method can include etching an opening at a bottom of the dielectric liner before depositing the polysilicon to provide ohmic contact to the semiconductor substrate.

First claim

The invention claimed is:

1. A method of fabricating an integrated circuit (IC), comprising:
etching a trench in a semiconductor substrate, the trench having a trench depth between 10 μm and 50 μm;
forming a dielectric liner along walls of said trench to form a dielectric lined trench; and
depositing in-situ doped polysilicon into said trench to form a dielectric lined polysilicon filled trench having a doped polysilicon filler.

2. The method of claim 1 , wherein said doped polysilicon filler has an average dopant concentration between 5×10 18 cm −3 and 1×10 21 cm −3 , and a 25° C. sheet resistance of ≦50 ohms/sq.

3. The method of claim 1 , wherein said semiconductor substrate is a bulk substrate material.

4. The method of claim 1 , further comprising etching an opening at a bottom portion of said dielectric liner before said depositing to provide an opening for an ohmic contact between said doped polysilicon filler and said semiconductor substrate.

5. The method of claim 1 , wherein said semiconductor substrate is boron doped and said in-situ doped polysilicon is boron doped so that said doped polysilicon filler is boron doped.

6. The method of claim 1 , wherein said depositing includes flowing BCl 3 gas in a flow range from 5 to 30 Standard Cubic Centimeters per Minute (sccm) along with at least one diluent gas so that said BCl 3 gas is diluted to less than 10% by volume.

7. The method of claim 6 , wherein said diluent gas comprises H 2 .

8. The method of claim 1 , wherein for said depositing uses a temperature range of 550° C. to 650 C and a pressure range from 100 mTorr to 400 mTorr.

9. An integrated circuit (IC), comprising:
a semiconductor substrate; and
a plurality of dielectric lined polysilicon filled trenches in said semiconductor substrate each having a doped polysilicon filler essentially void-free, and each having a trench depth between 10 μm and 50 μm.

10. The IC of claim 9 , wherein an average dopant concentration in said doped polysilicon filler is between 5×10 18 cm −3 and 5×10 21 cm −3 , and a 25° C. sheet resistance of said doped polysilicon filler is equal to or less than 50 ohms/sq.

11. The IC of claim 9 , wherein said semiconductor substrate is a bulk substrate material.

12. The IC of claim 9 , wherein each of said plurality of dielectric lined polysilicon filled trenches includes a bottom opening providing an ohmic contact between said doped polysilicon filler and said semiconductor substrate.

13. The IC of claim 12 , wherein said semiconductor substrate is boron doped, said doped polysilicon filler is boron doped, and a 25° C. sheet resistance of said doped polysilicon filler is less than or equal to 50 ohms/sq.

14. An integrated circuit (IC), comprising:
a semiconductor substrate; and
a plurality of dielectric lined polysilicon filled trenches in said semiconductor substrate each having:
a trench depth between 10 μm and 50 μm;
a doped polysilicon filler essentially void-free; and
a bottom opening providing an ohmic contact between said doped polysilicon filler and said semiconductor substrate.

Assignees

• Texas Instruments Inc

Inventors

• Srinivasan Bhaskar
• Le Khanh Quang
• White Collin
• Chevacharoenkul Sopa
• Norris Ashley
• Fischer Bernard John

Classifications

• H10W10/041 Primary

  of isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10W10/40

  Isolation regions comprising polycrystalline semiconductor materials · CPC title

• H10D64/0113

  the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H01L21/763

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic