Semiconductor device and manufacturing method of a semiconductor device

Patent metadata

Field	Value
Publication number	US-12419052-B2
Application number	US-202418614945-A
Country	US
Kind code	B2
Filing date	Mar 25, 2024
Priority date	Aug 10, 2018
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first well region;
a second well region over the first well region;
a source region over the second well region;
a stack structure over the source region;
a slit insulting structure separating the stack structure, the source region and the second well region into a first region and a second region; and
a source connection structure passing through the stack structure in the second region, wherein the source connection structure is physically contacted with the source region.

2. The semiconductor device of claim 1 , further comprising a well connection structure passing through the stack structure, the source region and the second well region in the first region, wherein the well connection structure is coupled to the first well region.

3. The semiconductor device of claim 1 , further comprising a channel layer passing through the stack structure, the source region and the second well region.

4. The semiconductor device of claim 3 , wherein the channel layer is coupled to the source region and the second well region.

5. The semiconductor device of claim 1 , further comprising an insulating pattern insulating the source connection structure from the second well region.

Assignees

• Sk Hynix Inc

Inventors

• Park In Su

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title