Semiconductor device and manufacturing method of a semiconductor device

Patent metadata

Field	Value
Publication number	US-10868035-B2
Application number	US-201916359568-A
Country	US
Kind code	B2
Filing date	Mar 20, 2019
Priority date	Aug 10, 2018
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A semiconductor device includes a stack structure, a channel layer passing through the stack structure, a memory layer enclosing the channel layer and including first and second openings which expose the channel layer, a well plate coupled to the channel layer through the first opening, and a source plate coupled to the channel layer through the second opening.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a stack structure;
a channel layer passing through the stack structure;
a memory layer enclosing the channel layer and including first and second openings which expose the channel layer;
a well plate coupled to the channel layer through the first opening; and
a source plate coupled to the channel layer through the second opening,
wherein the stack structure comprises:
sacrificial layers and first insulating layers alternately stacked with each other in a first region; and
conductive layers and the first insulating layers alternately stacked with each other in a second region.

2. The semiconductor device of claim 1 , further comprising:
a source connection structure passing through the stack structure and electrically coupled to the source plate; and
a well connection structure passing through the stack structure and electrically coupled to the well plate.

3. The semiconductor device of claim 1 , further comprising a slit insulating structure passing through the stack structure at a boundary between the first region and the second region.

4. The semiconductor device of claim 2 , wherein the source connection structure is disposed in the second region and the well connection structure is disposed in the first region.

5. The semiconductor device of claim 2 , wherein the source connection structure comprises:
a first conductive pattern coupled to the source plate; and
a second conductive pattern coupled to the first conductive pattern, wherein the second conductive pattern has a lower resistance than the first conductive pattern.

6. The semiconductor device of claim 1 , wherein the source plate is disposed above the well plate.

7. The semiconductor device of claim 1 , wherein the source plate is disposed under the well plate.

8. The semiconductor device of claim 1 , wherein the source plate comprises:
a first conductive layer; and
a second conductive layer formed on the first conductive layer.

9. The semiconductor device of claim 8 , wherein the first conductive layer includes a first protruding portion protruding from an upper surface of the first conductive layer and a second protruding portion protruding from a lower surface of the first conductive layer.

10. The semiconductor device of claim 9 , further comprising a source connection structure passing through the stack structure and coupled to the first protruding portion.

11. The semiconductor device of claim 9 , wherein the first conductive layer further includes a junction formed in the first protruding portion.

12. The semiconductor device of claim 1 , further comprising:
a source connection structure passing through the stack structure and electrically coupled to the source plate; and
an insulating spacer enclosing a sidewall of the source connection structure.

13. The semiconductor device of claim 12 , wherein the source connection structure passes through the source plate and extends beyond a lower surface of the source plate.

14. The semiconductor device of claim 12 , further comprising an insulating pattern disposed under the source connection structure, wherein the insulating pattern electrically insulates the source connection structure from the well plate.

15. A semiconductor device, comprising:
a base including a well region doped with an impurity;
a well plate on the base;
a source plate on the well plate;
an insulating layer interposed between the well plate and the source plate, wherein the insulating layer electrically insulates the well plate from the source plate;
a stack structure disposed above the source plate, wherein the stack structure comprises conductive layers and insulating layers alternately stacked with each other;
a source connection structure passing through the stack structure, wherein the source connection structure is electrically coupled to the source plate and electrically insulated from the conductive layers and the well plate; and
a well connection structure electrically coupled to the well plate and electrically insulated from the source plate and the conductive layers, wherein the well connection structure extends through the conductive layers and through the well plate into the well region.

Assignees

• Sk Hynix Inc

Inventors

• Park In Su

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/27

  using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials · CPC title