Gate driving circuit having a gating circuit, and driving method thereof

Patent metadata

Field	Value
Publication number	US-12417744-B2
Application number	US-202218288412-A
Country	US
Kind code	B2
Filing date	Dec 19, 2022
Priority date	Dec 19, 2022
Publication date	Sep 16, 2025
Grant date	Sep 16, 2025

Abstract

A driving circuit includes a driving signal generation circuit, a gating circuit, an output control circuit, an output circuit and a voltage control circuit; the driving signal generation circuit generates an Nth stage of driving signal, the output control circuit connects the first control node and the second node under the control of the potential of the first node; the gating circuit controls to write a gating input signal into the first node under the control of a gating control signal; the voltage control circuit controls a potential of the second node according to a potential of the first node; the output circuit connects the output driving terminal and the first voltage terminal under the control of the potential of the second node, and connects the output driving terminal and the second voltage terminal under the control of the potential of the third control node.

First claim

What is claimed is:

1. A driving circuit, comprising a driving signal generation circuit, an output control circuit, a gating circuit, a voltage control circuit and an output circuit; wherein
the driving signal generation circuit is electrically connected to a first control node, a second control node and an Nth stage of driving signal output terminal, is configured to generate and output an Nth stage of driving signal through the Nth stage of driving signal output terminal under the control of a potential of the first control node and a potential of the second control node;
the output control circuit is electrically connected to a first node, the first control node and a second node respectively, and is configured to control to connect the first control node and the second node under the control of a potential of the first node;
the gating circuit is electrically connected to the first node, a gating input terminal and a gating control terminal, and is configured to control to write a gating input signal provided by the gating input terminal into the first node under the control of a gating control signal provided by the gating control terminal;
the voltage control circuit is electrically connected to the first node and the second node respectively, and is configured to control a potential of the second node according to the potential of the first node;
the output circuit is electrically connected to the second node, a third control node, a first voltage terminal, a second voltage terminal and an output driving terminal respectively, is configured to control to connect the output driving terminal and the first voltage terminal under the control of the potential of the second node, and control to connect the output driving terminal and the second voltage terminal under the control of a potential of the third control node;
the third control node and the second control node are different nodes, N is a positive integer.

2. The driving circuit according to claim 1 , wherein the gating circuit is configured to control to write the gating input signal provided by the gating input terminal into the first node when a potential of the (N-1)th stage of third node is a second voltage and a potential of the Nth stage of driving signal is the second voltage.

3. The driving circuit according to claim 1 , wherein the gating circuit includes a first transistor; a gate electrode of the first transistor is electrically connected to the gating control terminal, and a first electrode of the first transistor is electrically connected to the first node, a second electrode of the first transistor is electrically connected to the gating input terminal.

4. The driving circuit according to claim 1 , wherein the gating control terminal includes a first gating control terminal and a second gating control terminal; the gating circuit includes a first transistor and a second transistor;
a gate electrode of the first transistor is electrically connected to the first gating control terminal, a first electrode of the first transistor is electrically connected to the first node, and a second electrode of the first transistor is electrically connected to a first electrode of the second transistor;
a gate electrode of the second transistor is electrically connected to the second gating control terminal, and a second electrode of the second transistor is electrically connected to the gating input terminal;
the first gating control terminal is the Nth stage of driving signal output terminal, the second gating control terminal is an (N-1)th stage of third node, and both the first transistor and the second transistor are p-type transistors; or,
the first gating control terminal is the (N-1)th stage of third node, the second gating control terminal is the Nth stage of driving signal output terminal, and the first transistor and the second transistor are p-type transistors; or,
the first gating control terminal is the (N-1) th stage of driving signal output terminal, the second gating control terminal is the Nth stage of driving signal output terminal, the first transistor is an n-type transistor, and the second transistor is a p-type transistor; or,
the first gating control terminal is the Nth stage of driving signal output terminal, the second gating control terminal is the (N-1)th stage of driving signal output terminal, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or,
the first gating control terminal is connected to an inversion signal of the (N-1)th stage of driving signal, the second gating control terminal is the Nth stage of driving signal output terminal, the first transistor and the second transistor are both p-type transistors; or,
the first gating control terminal is the Nth stage of driving signal output terminal, and the second gating control terminal is connected to the inversion signal of the (N-1)th stage of driving signal; the first transistor and the second transistor are both p-type transistors; or,
the first gating control terminal is the (N-1) th stage of driving signal terminal, the second gating control terminal is connected to an inversion signal of the Nth stage of driving signal, and the first transistor and the second transistor are both n-type transistors; or,
the first gating control terminal is connected to the inversion signal of the Nth stage of driving signal, the second gating control terminal is the (N-1) th stage of driving signal terminal, and the first transistor and the second transistor are both n-type transistors.

5. The driving circuit according to claim 1 , wherein the output control circuit includes a third transistor;
a gate electrode of the third transistor is electrically connected to the first node, a first electrode of the third transistor is electrically connected to the first control node, and a second electrode of the third transistor is electrically connected to the second node;
or
wherein the voltage control circuit includes a first capacitor;
a first terminal of the first capacitor is electrically connected to the first node, and a second terminal of the first capacitor is electrically connected to the second node:
or
the driving circuit further includes a second node control circuit; wherein
the second node control circuit is electrically connected to a third control node, a second node and a first voltage terminal, and is configured to control to connect the second node and the first voltage terminal under the control of a potential of the third control node,
wherein the second node control circuit comprises a fourth transistor;
a gate electrode of the fourth transistor is electrically connected to the third control node, a first electrode of the fourth transistor is electrically connected to the second node, and a second electrode of the fourth transistor is connected to the first voltage terminal;
or
wherein the output circuit includes a fifth transistor, a sixth transistor and a second capacitor;
a gate electrode of the fifth transistor is electrically connected to the second node, a first electrode of the fifth transistor is electrically connected to the first voltage terminal, and a second electrode of the fifth transistor is electrically connected to the output driving terminal:
a gate electrode of the sixth transistor is electrically connected to the third control node. a first electrode of the sixth transistor is electrically connected to the output driving terminal, and a second electrode of the sixth transistor is connected to the second voltage terminal;
a first terminal of the second capacitor is electrically connected to the second node, and a second terminal of the second capacitor is electrically connected to the first voltage terminal.

6. The driving circuit according to claim 1 , furthe

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Yu Ziyang
• Qiu Haijun
• Hu Ming
• Jiang Zhiliang
• Cheng Tianyi
• Wu Jianpeng
• Zhao Erjin
• Wang Mengqi
• Chen Wenbo
• Liu Cong
• Xu Qian

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title