Scan driver and display device having the same

Patent metadata

Field	Value
Publication number	US-2020184898-A1
Application number	US-201916707994-A
Country	US
Kind code	A1
Filing date	Dec 9, 2019
Priority date	Dec 10, 2018
Publication date	Jun 11, 2020
Grant date	—

Abstract

A stage of a scan driver includes: a first driving controller for controlling a voltage of a first node and a voltage of a second node; a second driving controller for controlling a voltage of a first driving node, based on a sensing-on signal, a next carry signal, a first control clock signal, a second control clock signal, the voltage of the first node, and a voltage of a sampling node, and controlling a voltage of a second driving node, based on the voltage of the sampling node and the voltage of the first driving node; an output buffer for outputting a carry signal, the first scan signal, and the second scan signal; and a coupling controller. The second driving controller maintains the voltage of the first driving node as a gate-off voltage in response to the voltage of the second driving node and a third control clock signal.

First claim

What is claimed is:

1 . A scan driver comprising:
a plurality of stages each configured to output a first scan signal and a second scan signal, each of the plurality of stages comprising: a first driving controller configured to control a voltage of a first node and a voltage of a second node in response to a previous carry signal; a second driving controller configured to control a voltage of a first driving node, based on a sensing-on signal, a next carry signal, a first control clock signal, a second control clock signal, the voltage of the first node, and a voltage of a sampling node, and control a voltage of a second driving node, based on the voltage of the sampling node and the voltage of the first driving node; an output buffer configured to output a carry signal in response to the voltage of the first node and the voltage of the second node, and output the first scan signal and the second scan signal in response to the voltage of the first driving node and the voltage of the second driving node; and a coupling controller configured to electrically couple the first node and the first driving node to each other and electrically couple the second node and the second driving node to each other, in response to a display-on signal, wherein the second driving controller is configured to maintain the voltage of the first driving node as a gate-off voltage in response to the voltage of the second driving node and a third control clock signal, wherein the previous carry signal refers to a carry signal from a previous stage, and wherein the next carry signal refers to a carry signal from a next stage.

2 . The scan driver of claim 1 , wherein the second driving controller includes:
a fourteenth transistor and a fifteenth transistor coupled in series between a carry output terminal outputting the carry signal and the first driving node, wherein a gate electrode of the fourteenth transistor receives the third control clock signal, and a gate electrode of the fifteenth transistor is coupled to the second driving node.

3 . The scan driver of claim 2 , configured to receive a gate-on voltage as the third control clock signal in a vertical blank period, and maintained until a partial period of a display period continued to the vertical blank period.

4 . The scan driver of claim 2 , wherein the second driving controller is configured to maintain a gate-off voltage to the first driving node in response to the fourteenth and fifteenth transistors being turned on.

5 . The scan driver of claim 2 , wherein the second driving controller comprises:
an eighth transistor coupled between an input terminal to which the next carry signal is applied and the sampling node, the eighth comprising a gate electrode receiving the sensing-on signal; a ninth transistor and a tenth transistor coupled in series between a first control clock terminal to which the first control clock signal is applied and the first driving node; and an eleventh transistor coupled between a carry output terminal outputting the carry signal and a third node between the ninth and tenth transistors, the eleventh transistor comprising a gate electrode coupled to the carry output terminal.

6 . The scan driver of claim 5 , wherein a gate electrode of the ninth transistor is coupled to the sampling node, and
a gate electrode of the tenth transistor is coupled to a second control clock terminal to which the second control clock signal is applied.

7 . The scan driver of claim 6 , wherein the second control clock signal has a gate-on voltage in at least a portion of a vertical blank period, and maintains a gate-off voltage during a display period.

8 . The scan driver of claim 7 , wherein the entire gate-on voltage period of the second control clock signal overlaps with at least a portion of a gate-on voltage period of the first control clock signal.

9 . The scan driver of claim 5 , wherein gate electrodes of the ninth and tenth transistors are commonly coupled to the sampling node.

10 . The scan driver of claim 5 , wherein the eighth transistor comprises: a plurality of eighth transistors coupled in series between the input terminal and the sampling node,
wherein gate electrodes of each of the plurality of eighth transistors commonly receive the sensing-on signal.

11 . The scan driver of claim 10 , wherein the second driving controller further comprises: a twenty-seventh transistor coupled between a first power terminal to which a first power source is supplied and a common node between the plurality of eighth transistors, the twenty-seventh transistor comprising a gate electrode coupled to the sampling node.

12 . The scan driver of claim 2 , wherein the second driving controller further comprises:
a capacitor coupled between a second power terminal to which a second power source is applied and the sampling node; a twelfth transistor and a thirteenth transistor coupled in series between a third power terminal to which a third power source is applied and the second driving node; and a twenty-fifth transistor coupled between a first power terminal to which a first power source is supplied and an intermediate node between the twelfth transistor and the thirteenth transistor, the twenty-fifth transistor comprising a gate electrode coupled to the second driving node, wherein the twelfth transistor comprises a gate electrode coupled to the sampling node, and the thirteenth transistor comprises a gate electrode coupled to the first driving node.

13 . The scan driver of claim 1 , wherein the first driving controller comprises:
a first transistor coupled between a first power terminal to which a first power source is applied and the first node, the first transistor comprising a gate electrode receiving the previous carry signal or a scan start signal; a second transistor and a third transistor coupled in series between the first node and a carry output terminal outputting the carry signal; a fourth transistor coupled between the first node and the carry output terminal, the fourth transistor comprising a gate electrode receiving the next carry signal; a fifth transistor coupled between a first clock terminal to which a first clock signal is applied and the second node, the fifth transistor comprising a gate electrode coupled to the first node; a sixth transistor coupled between the first power terminal and the second node, the sixth transistor comprising a gate electrode coupled to the first clock terminal; and a seventh transistor coupled between the first power terminal and the second node.

14 . The scan driver of claim 13 , wherein the seventh transistor comprises a gate electrode receiving the first control clock signal.

15 . The scan driver of claim 13 , wherein the fifth transistor comprises a plurality of fifth transistors coupled in series between the first clock terminal and the second node,
wherein gate electrodes of the plurality of fifth transistors are commonly coupled to the first node, wherein the first driving controller further comprises: a twenty-fourth transistor coupled between the first power terminal and a common node between the plurality of fifth transistors, the twenty-fourth transistor comprising a gate electrode coupled to the second node.

16 . The scan driver of claim 1 , wherein the output buffer comprises:
a sixteenth transistor coupled between a second clock terminal to which a clock signal is supplied and a carry output terminal outputting the carry signal, the sixteenth transistor comprising a gate electrode coupled to the first node; a seventeenth transistor c

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Yang Hwa
• Park Jun Hyun
• Kim Dong Woo
• Jo Kang Moon
• Moon Sung Jae
• Lee An Su
• Choi Woong Sik

Classifications

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2320/0295

  by monitoring each display pixel · CPC title