Scan driver and display panel using the same

Patent metadata

Field	Value
Publication number	US-2016148556-A1
Application number	US-201514921000-A
Country	US
Kind code	A1
Filing date	Oct 23, 2015
Priority date	Nov 26, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

The present invention provides a scan driver and a display using the same. The scan driver includes multiple stages of driving units. The driving units are controlled by a start signal, a clock signal and at least one selection signal. The i th stage of the driving unit includes a shift register and a de-multiplexer. The shift register generates a scan signal according to the clock signal and a trigger signal. The de-multiplexer selectively outputs the scan signal to multiple scan lines according to the at least one selection signal. The trigger signal of the 1 st stage of the driving unit is the start signal, and the trigger signal of the (i+1) th stage of the driving unit is the scan signal of the i th stage of the driving unit.

First claim

What is claimed is:

1 . A display panel, comprising:
a thin film transistor array substrate; a first display region, comprising a plurality of first row pixel circuits; and a scan driver, comprising:
a plurality of stages of first driving units, controlled by a first start signal, a clock signal, and at least one selection signal, wherein each first driving unit comprises:
a first shift register, generating a scan signal according to the clock signal and a trigger signal; and
a first de-multiplexer, selectively outputting the scan signal to a plurality of scan lines according to the at least one selection signal;

wherein the trigger signal of the 1 st stage of the first driving unit is the first start signal, and the trigger signal of the (i+1) th stage of the first driving unit is the scan signal of the i th stage of the first driving unit, with i being a positive integer greater than or equal to 1.

2 . The display panel according to claim 1 , wherein for each first driving unit, the de-multiplexer selectively outputs either the scan signal or a cutoff voltage to the scan lines respectively according to the at least one selection signal.

3 . The display panel according to claim 1 , wherein a number of the scan lines outputted from each first driving unit is the same, and a number of the at least one selection signal is related to the number of the scan lines outputted from each first driving unit.

4 . The display panel according to claim 1 , wherein the scan lines outputted from each first driving unit are configured to drive adjacent first row pixel circuits in the first display region.

5 . The display panel according to claim 1 , further comprising:
a second display region, comprising a plurality of second row pixel circuits; wherein the scan driver further comprises:
a plurality of stages of second driving units, controlled by a second start signal, the clock signal, and the at least one selection signal, wherein the second driving unit comprises:
a second shift register, generating a scan signal according to the clock signal and a trigger signal; and
a second de-multiplexer, selectively outputting the scan signal to a plurality of scan lines according to the at least one selection signal;

wherein the trigger signal of the 1 st stage of the second driving unit is the second start signal, and the trigger signal of the (j+1) th stage of the second driving unit is the scan signal of the j th stage of the second driving unit, with j being a positive integer greater than or equal to 1.

6 . The display panel according to claim 5 , wherein a number of the scan lines outputted from each second driving unit is the same, and is equal to the number of the scan lines outputted from each first driving unit, and a number of the at least one selection signal is related to the number of the scan lines outputted from each first driving unit.

7 . The display panel according to claim 5 , wherein the scan driver further comprises:
a plurality of stages of compensation driving units, controlled by a compensation start signal, the clock signal, and the at least one selection signal, wherein each compensation driving unit comprises:
a third shift register, generating a compensation signal according to the clock signal and a trigger signal; and
a third de-multiplexer, selectively outputting the compensation signal to a plurality of compensation lines according to the at least one selection signal;
wherein the trigger signal of the 1 st stage of the compensation driving unit is the compensation start signal, and the trigger signal of the (k+1) th stage of the compensation driving unit is the compensation signal of the k th stage of the compensation driving unit, with k being a positive integer greater than or equal to 1.

8 . The display panel according to claim 7 , wherein each compensation line outputted from each compensation driving unit is configured to compensate one of the first row pixel circuits.

9 . The display panel according to claim 7 , wherein each compensation line outputted from each compensation driving unit is configured to compensate at least two of the first row pixel circuits simultaneously.

10 . A scan driver, comprising:
a plurality of stages of first driving units, controlled by a first start signal, a clock signal, and at least one selection signal, wherein at least one of the first driving units comprises:
a shift register, generating a first scan signal according to the clock signal and a trigger signal; and
a de-multiplexer, selectively outputting the first scan signal to a plurality of scan lines according to the at least one selection signal;
wherein the trigger signal of the 1 st stage of the first driving unit is the first start signal, and the trigger signal of the (i+1) th stage of the first driving unit is the scan signal of the i th stage of the first driving unit, with i being a positive integer greater than or equal to 1.

Assignees

• Innolux Corp

Inventors

• Tseng Ming-Chun
• Chen Chun-Yu
• Hsu Hung-Lin
• Huang Chien-Hsiang

Classifications

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/0218

  with collection of electrodes in groups for n-dimensional addressing · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title