Apparatus and method for efficient memory renaming prediction using virtual registers

Patent metadata

Field	Value
Publication number	US-9552169-B2
Application number	US-201514706936-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	May 7, 2015
Publication date	Jan 24, 2017
Grant date	Jan 24, 2017

Abstract

A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively; a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

First claim

What is claimed is:

1. An apparatus comprising:
a memory execution unit (MEU) to perform store and load operations to store data to memory and load data from memory, respectively;
a plurality of memory rename (MRN) registers assigned to store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and
at least one MRN predictor comprising a data structure to allocate virtual memory rename (VMRN) registers to each of the MRN registers, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively, to determine a current VMRN register associated with the load and/or store operation.

2. The apparatus as in claim 1 wherein the data structure comprises a table with a different entry for each MRN register, each entry in the table associating its MRN register with a VMRN register.

3. The apparatus as in claim 2 further comprising:
a macroinstruction translation engine (MITE) comprising decode logic to decode macroinstructions into a plurality of microoperations (uops) including store and load uops,
wherein the at least one MRN predictor includes a MITE-MRN predictor comprising the table to associate an MRN register assigned to a store and/or load uop with a VMRN register.

4. The apparatus as in claim 3 further comprising:
a uop cache to cache uops prior to execution in accordance with a cache management policy, the MITE-MRN predictor to update store uop and/or load uop entries in the uop cache with memory renaming information including a current MRN register and current VMRN register associated with the MRN register.

5. The apparatus as in claim 4 further comprising:
a loop stream detector (LSD) communicatively coupled to an instruction decode queue (IDQ) to queue store and/or load uops prior to execution, the LSD to detect loops in program code and execute uops associated with the loops from the IDQ, wherein the IDQ further comprises an IDQ-MRN predictor comprising a data structure to extend entries in the IDQ to include mappings of MRN registers with VMRN registers associated store and/or load uops.

6. The apparatus as in claim 5 wherein in response to an allocate event from the MEU the MITE-MRN predictor is to associate a new VMRN register with an MRN register within the table and/or the IDQ-MRN predictor is to associate a new VMRN with an MRN register within its data structure for store and/or load uops stored within the IDQ.

7. The apparatus as in claim 6 further comprising:
a state machine associated with the table and/or the data structure, the state machine to be placed in a more confident state in response to a promote event received from the MEU, the MEU to generate the promote event for each load for which data is successfully read from an MRN register associated with the load.

8. The apparatus as in claim 7 wherein the state machine comprises a confidence counter value maintained within the table and/or the data structure, the confidence counter value to be incremented in response to a promote event received from the MEU, the MEU to generate the promote event for each load for which data is successfully read from an MRN register associated with the load.

9. The apparatus as in claim 7 wherein the state machine is configured to be placed in a less confident state in response to detecting a load for which correct data was not available in a corresponding MRN register.

10. The apparatus as in claim 9 wherein the state machine comprises a and wherein a confidence counter value is to be decremented or set to 0 in response to detecting a load for which correct data was not available in a corresponding MRN register.

11. The method as in claim 8 wherein the MITE-MRN predictor is to set a rename indication in the uop cache in response to a confidence counter value above a specified threshold.

12. The apparatus as in claim 11 wherein fetched stores and loads which hit in the uop-cache receive an indication of the MRN register, VMRN register, and rename indication from the uop-cache.

13. The apparatus as in claim 12 wherein fetched stores and loads which miss in the uop-cache look up the MITE-MRN predictor and, in case of a hit, the MITE-MRN predictor attaches to the store/load an MRN register, VMRN register, and rename indication if the confidence counter greater than a threshold.

14. A method comprising:
performing store and load operations in a memory execution unit (MEU) to store data to memory and load data from memory, respectively;
assigning a plurality of memory rename (MRN) registers to the store and load operations, each MRN register to store data associated with a store operation so that the data is available for a subsequent load operation; and
allocating virtual memory rename (VMRN) registers to each of the MRN registers with at least one MRN predictor comprising a data structure, the MRN predictor to query the data structure in response to a load and/or store operation using a value identifying the MRN register assigned to the load and/or store operation, respectively; to determine a current VMRN register associated with the load and/or store operation.

15. The method as in claim 12 wherein the data structure comprises a table with a different entry for each MRN register, each entry in the table associating its MRN register with a VMRN register.

16. The method as in claim 13 further comprising:
decoding macroinstructions with decode logic in a macroinstruction translation engine (MITE), the macroinstructions decoded into a plurality of microoperations (uops) including store and load uops,
wherein at least one MRN predictor includes a MITE-MRN predictor comprising the table to associate an MRN register assigned to a store and/or load uop with a VMRN register.

17. The method as in claim 14 further comprising:
caching uops in a uop cache prior to execution in accordance with a cache management policy, the MITE-MRN predictor to update store uop and/or load uop entries in the uop cache with memory renaming information including a current MRN register and current VMRN register associated with the MRN register.

18. The method as in claim 17 further comprising:
queuing store and/or load uops prior to execution in an instruction decode queue (IDQ) communicatively coupled to a loop stream detector (LSD), the LSD to detect loops in program code and execute uops associated with the loops from the IDQ, wherein the IDQ further comprises an IDQ-MRN predictor comprising a data structure to extend entries in the IDQ to include mappings of MRN registers with VMRN registers associated store and/or load uops.

19. The method as in claim 18 wherein in response to an allocate event from the MEU the MITE-MRN predictor is to associate a new VMRN register with an MRN register within the table and/or the IDQ-MRN predictor is to associate a new VMRN with an MRN register within its data structure for store and/or load uops stored within the IDQ.

20. The method as in claim 19 further comprising:
implementing a state machine associated with the table and/or the data structure, the state machine to be placed in a more confident state in response to a promote event received from the MEU, the MEU to generate the promote event for each load for which data is successfully read from an MRN register associated with the load.

21. The method as in claim 20 wherein the state m

Assignees

• Intel Corp

Inventors

• Rappoport Lihu
• Stark Jared W
• Garifullin Kamil
• Sala Franck
• Kryukov Pavel I
• Shwartsman Stanislav

Classifications

• G06F3/06

  Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers} · CPC title

• G06F9/3834

  Maintaining memory consistency · CPC title

• G06F9/3832

  Value prediction for operands; operand history buffers · CPC title

• G06F3/0671

  In-line storage system · CPC title

• G06F9/384

  Register renaming · CPC title