Three dimensional memory device and method of making thereof by forming channel and memory film after word line replacement

Patent metadata

Field	Value
Publication number	US-12414296-B2
Application number	US-202117523418-A
Country	US
Kind code	B2
Filing date	Nov 10, 2021
Priority date	Apr 29, 2021
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, forming a sacrificial memory opening fill structure in the memory opening, replacing the sacrificial material layers with electrically conductive layers, removing the sacrificial memory opening fill structure selective to the electrically conductive layers, and forming a memory opening fill structure the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure. The memory opening fill structure includes a memory film and a vertical semiconductor channel.

First claim

The invention claimed is:

1. A method of forming a three-dimensional memory device, comprising:
forming an alternating stack of insulating layers and sacrificial material layers over a substrate;
forming a memory opening extending through the alternating stack;
forming a sacrificial memory opening fill structure in the memory opening;
replacing the sacrificial material layers with electrically conductive layers;
removing the sacrificial memory opening fill structure selective to the electrically conductive layers; and
forming a memory opening fill structure in the memory opening after replacing the sacrificial material layers with electrically conductive layers and after removing the sacrificial memory opening fill structure, wherein the memory opening fill structure comprises a memory film and a vertical semiconductor channel.

2. The method of claim 1 , wherein a memory cavity is formed within a volume of the memory opening after the step of removing the sacrificial memory opening fill structure.

3. The method of claim 2 , further comprising:
laterally recessing the insulating layers selective to the electrically conductive layers around the memory cavity; and
forming a vertical stack of tubular dielectric spacers on recessed sidewalls of the insulating layers in the memory cavity.

4. The method of claim 3 , further comprising anisotropically etching portions of the electrically conductive layers that are not covered by the vertical stack of tubular dielectric spacers.

5. The method of claim 4 , wherein the anisotropically etching portions of the electrically conductive layers comprises performing an anisotropic etch process during formation of the vertical stack of tubular dielectric spacers and prior to formation of the memory opening fill structure.

6. The method of claim 4 , wherein the anisotropically etching portions of the electrically conductive layers comprises performing an anisotropic etch process after formation of the vertical stack of tubular dielectric spacers and prior to formation of the memory opening fill structure.

7. The method of claim 4 , further comprising:
forming a backside trench;
forming backside recesses by removing the sacrificial material layers through the backside trench selective to the insulating layers and the sacrificial memory opening fill structure;
depositing a metallic liner material in the backside recesses through the backside trench; and
depositing a metal in remaining volumes of the backside recesses through the backside trench, wherein each of the electrically conductive layers comprises a metallic fill material layer comprising a portion of the metal, and a metallic liner comprising a portion of the metallic liner material.

8. The method of claim 7 , wherein sidewalls of the metallic fill material layers are exposed upon anisotropically etching the portions of the electrically conductive layers that are not covered by the vertical stack of tubular dielectric spacers.

9. The method of claim 4 , wherein:
each of the electrically conductive layers comprises a metallic fill material layer embedded within a metallic liner prior to the anisotropic etching;
the anisotropic etching removes vertically-extending portions of the metallic liners; and
each of the metallic liners is divided into a respective upper metallic liner and a lower metallic liner by the anisotropic etch process.

10. The method of claim 9 , wherein:
one of the electrically conductive layers comprises a seam or air gap prior to the anisotropic etch process;
the seam or air gap is laterally spaced from the memory cavity by a portion of the metallic fill material layer of the one of the electrically conductive layers after the anisotropic etching.

Assignees

• Sandisk Technologies Llc
• Sandisk Technologies Inc

Inventors

• Mukae Yusuke
• Takeguchi Naoki
• Terasawa Yujin
• Hinoue Tatsuya
• Said Ramy Nashed Bassely

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10D64/033

  comprising ferroelectric layers · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B51/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title