Hybrid embedded package

Patent metadata

Field	Value
Publication number	US-12412797-B2
Application number	US-202217973920-A
Country	US
Kind code	B2
Filing date	Oct 26, 2022
Priority date	Oct 14, 2020
Publication date	Sep 9, 2025
Grant date	Sep 9, 2025

Abstract

A method of producing a semiconductor package includes providing a substrate formed of electrically insulating material and including a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die including a first conductive terminal that faces the die mounting surface, providing a second semiconductor die that includes a first conductive terminal, and mounting the second semiconductor die on the die mounting surface such that the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface, a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed, and the second semiconductor die partially overlaps with the first semiconductor die.

First claim

What is claimed is:

1. A method of producing a semiconductor package, the method comprising:
providing a substrate formed of electrically insulating material and comprising: a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die comprising a first conductive terminal that faces the die mounting surface;
providing a second semiconductor die that comprises a first conductive terminal; and
mounting the second semiconductor die on the die mounting surface such that:
the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface;
a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed; and
the second semiconductor die partially overlaps with the first semiconductor die,
wherein the second semiconductor die comprises a switching device, wherein the first semiconductor die comprises a driver that is configured to control the switching device, and wherein the first electrical connection is a connection between an output terminal of the driver and a control terminal of the switching device, and
wherein the method further comprises mounting a fourth semiconductor die on the die mounting surface, wherein the fourth semiconductor die does not overlap with the first semiconductor die, and wherein the fourth semiconductor die comprises a passive electrical component.

2. The method of claim 1 , wherein mounting the second semiconductor die comprises arranging the second semiconductor die such that the first conductive terminals of the first and second semiconductor dies are aligned with one another, and wherein the first electrical connection comprises one or more conductive structures that directly vertically extend between the first conductive terminals of the first and second semiconductor dies.

3. The method of claim 2 , wherein the substrate is provided to comprise a first bond pad at the die mounting surface and a first conductive via connected between the first bond pad and the first conductive terminal of the first semiconductor die, and wherein mounting the second semiconductor die on the die mounting surface comprises arranging a first conductive pillar or solder bump between the first bond pad and the first conductive terminal of the second semiconductor die.

4. The method of claim 3 , wherein the substrate further comprises a structured metallization layer that is disposed on the die mounting surface and comprises a plurality of islands that are physically isolated from one another, wherein the first electrical connection further comprises a first one of the islands, and wherein the first one of the islands is completely contained within an areal footprint of the second semiconductor die.

5. The method of claim 4 , wherein the substrate is a laminate substrate.

6. The method of claim 5 , further comprising forming an electrically insulating encapsulant body on top of the die mounting surface that encapsulates the second semiconductor die.

7. The method of claim 1 , further comprising: forming an electrically insulating encapsulant body on top of the die mounting surface that encapsulates the second semiconductor die.

8. A method of producing a semiconductor package, the method comprising:
providing a substrate formed of electrically insulating material and comprising: a die mounting surface, and a first semiconductor die embedded within the substrate, the first semiconductor die comprising a first conductive terminal that faces the die mounting surface;
providing a second semiconductor die that comprises a first conductive terminal; and
mounting the second semiconductor die on the die mounting surface such that:
the first conductive terminal of the second semiconductor die faces and is spaced apart from the die mounting surface;
a first electrical connection that directly connects the first conductive terminals of the first and second semiconductor dies together is formed; and
the second semiconductor die partially overlaps with the first semiconductor die,
wherein the second semiconductor die comprises a switching device, wherein the first semiconductor die comprises a driver that is configured to control the switching device, and wherein the first electrical connection is a connection between an output terminal of the driver and a control terminal of the switching device.

Assignees

• Infineon Technologies Ag

Inventors

• Woetzel Stefan
• Ng Chee Yang

Classifications

• H10W74/131

  the semiconductor body being only partially enclosed · CPC title

• H10W70/614 Primary

  the multiple chips being integrally enclosed · CPC title

• H10W70/655

  Fan-out layouts · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title