Semiconductor device and electronic system

Patent metadata

Field	Value
Publication number	US-12408346-B2
Application number	US-202418760980-A
Country	US
Kind code	B2
Filing date	Jul 1, 2024
Priority date	Aug 10, 2020
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A semiconductor device includes a lower structure including a peripheral circuit, a lower insulating structure covering the peripheral circuit, and a pattern structure on the lower insulating structure; a stack structure including interlayer insulating layers and horizontal layers alternately stacked on the lower structure, wherein the horizontal layers include gate horizontal layers in a gate region of the stack structure and first insulating horizontal layers in a first insulating region of the stack structure; a memory vertical structure including a portion penetrating the gate horizontal layers; dummy vertical structures including a portion penetrating the gate horizontal layers; a first peripheral contact plug including a portion penetrating the first insulating region; and gate contact plugs on gate pads of the gate horizontal layers, wherein upper surface of the gate contact plugs and the first peripheral contact plugs are coplanar with each other, wherein the memory vertical structure and the dummy vertical structure are contacting the pattern structure, and wherein at least one of the dummy vertical structures extend further into the pattern structure than the memory vertical structure in a downward direction.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a lower structure including a peripheral circuit;
a stack structure on the lower structure and including a first stack portion and a second stack portion, wherein the first stack portion includes first interlayer insulating layers and gate conductive layers alternately stacked in a vertical direction, and the second stack portion includes second interlayer insulating layers and third interlayer insulating layers alternately stacked in the vertical direction;
a vertical memory structure penetrating through the first stack portion in the vertical direction;
a capping insulating layer on the stack structure;
a peripheral contact plug penetrating through the capping insulating layer and the second stack portion in the vertical direction; and
gate contact plugs in contact with gate pads of the gate conductive layers,
wherein the first interlayer insulating layers and the second interlayer insulating layers include a first material,
wherein the third interlayer insulating layers include a second material different from the first material,
wherein the peripheral contact plug includes:
an upper plug portion penetrating the capping insulating layer and extending downward;
a lower plug portion at a lower level than a lowermost third interlayer insulating layer among the third interlayer insulating layers; and
an intermediate plug portion between the upper plug portion and the lower plug portion,

wherein the intermediate plug portion penetrates the lowermost third interlayer insulating layer and extends upward,
wherein the upper plug portion has a first upper side surface and a second upper side surface opposing each other in a first horizontal direction,
wherein the intermediate plug portion has a first intermediate side surface and a second intermediate side surface opposing each other in the first horizontal direction,
wherein a width of the upper plug portion is greater than a width of the intermediate plug portion,
wherein a side surface of the peripheral contact plug includes a bent portion extending from the first intermediate side surface of the intermediate plug portion toward the first upper side surface of the upper plug portion, and
wherein at least a portion of the bent portion of the side surface of the peripheral contact plug is at a lower level than an upper surface of an uppermost third interlayer insulating layer among the third interlayer insulating layers.

2. The semiconductor device of claim 1 ,
wherein a first central axis of the upper plug portion and a second central axis of the intermediate plug portion are misaligned.

3. The semiconductor device of claim 2 ,
wherein the second central axis of the intermediate plug portion and a third central axis of the lower plug portion are aligned.

4. The semiconductor device of claim 1 ,
wherein the peripheral contact plug is in contact with the third interlayer insulating layers.

5. The semiconductor device of claim 1 ,
wherein a lower end of the first upper side surface of the upper plug portion is at a lower level than the upper surface of the uppermost third interlayer insulating layer.

6. The semiconductor device of claim 1 ,
wherein a lower end of the first upper side surface of the upper plug portion is at a higher level than a lower surface of the uppermost third interlayer insulating layer.

7. The semiconductor device of claim 1 ,
wherein an upper surface of the peripheral contact plug is at a higher level than an upper surface of the vertical memory structure.

8. The semiconductor device of claim 1 ,
wherein the peripheral contact plug is a plug conductive pattern and a conductive liner layer covering a side surface and a lower surface of the plug conductive pattern.

9. The semiconductor device of claim 1 , further comprising:
a bit line overlapping with the vertical memory structure and the peripheral contact plug;
a first contact plug between the bit line and the vertical memory structure; and
a second contact plug between the bit line and the peripheral contact plug.

10. The semiconductor device of claim 1 ,
wherein the vertical memory structure includes:
an insulating core pattern;
a channel layer on a side surface of the insulating core pattern; and
a data storage structure on an external surface of the channel layer.

11. The semiconductor device of claim 1 ,
wherein the first stack portion of the stack structure includes a lower stack structure and an upper stack structure on the lower stack structure, and
wherein a side surface of the vertical memory structure includes a bent portion at a level between an uppermost gate conductive layer among the gate conductive layers of the lower stack structure and a lowermost gate conductive layer among the gate conductive layers of the upper stack structure.

12. The semiconductor device of claim 1 ,
wherein the lower structure further includes:
a lower insulating structure covering the peripheral circuit;
a pattern structure on the lower insulating structure;
a pad pattern in the lower insulating structure; and
a gap-fill insulating layer penetrating the pattern structure and overlapping the pad pattern,

wherein the pattern structure includes a polysilicon layer, and
wherein the vertical memory structure is in contact with the polysilicon layer.

13. The semiconductor device of claim 12 ,
wherein the lower plug portion of the peripheral contact plug extends downwardly from the intermediate plug portion to penetrate the gap-fill insulating layer and contact the pad pattern.

14. The semiconductor device of claim 13 ,
wherein the lower insulating structure includes:
a first lower insulating layer at least partially surrounding a side surface of the pad pattern;
an etch stop layer on the first lower insulating layer and the pad pattern; and
a second lower insulating layer on the etch stop layer,

wherein the etch stop layer includes a material different from a material of the second lower insulating layer,
wherein a thickness of the etch stop layer is less than a thickness of the second lower insulating layer, and
wherein the lower plug portion of the peripheral contact plug penetrates the second lower insulating layer and the etch stop layer to contact the pad pattern.

15. The semiconductor device of claim 14 , wherein the lower plug portion of the peripheral contact plug extends further downwardly from the upper surface of the pad pattern into the pad pattern, and
a vertical height of the lower plug portion extending from the upper surface of the pad pattern into the pad pattern is greater than a thickness of the etch stop layer.

16. The semiconductor device of claim 1 ,
wherein the lower structure further includes a buffer conductive pattern between a pad pattern and the lower plug portion of the peripheral contact plug.

17. The semiconductor device of claim 16 ,
wherein the vertical memory structure is in contact with a pattern structure, and
wherein at least a portion of the buffer conductive pattern is at the same level as at least a portion of the pattern structure.

18. An electronic system, comprising:
a main substrate;
a semiconductor device on the main substrate; and
a controller electrically connected to the semiconductor device,
wherein the semiconductor device includes:
a lower structure including a peripheral circuit;
a stack structure on the lower structure and including a first stack portion and a second stack portion, wherein the first stack portion includes first interlayer

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sim Jaeryong
• Kang Shinhwan
• Han Jeehoon

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title