Electronic device and method of forming electronic device

Patent metadata

Field	Value
Publication number	US-12408269-B2
Application number	US-202217890242-A
Country	US
Kind code	B2
Filing date	Aug 17, 2022
Priority date	Jun 13, 2022
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

An electronic device includes a first electronic unit, a second electronic unit, a bonding pad, an insulating layer and a circuit layer. The bonding pad is disposed between the first electronic unit and the second electronic unit. The insulating layer is disposed corresponding to the first electronic unit, to the second electronic unit and to the bonding pad. The first electronic unit is electrically connected with the second electronic unit through the circuit layer and through the bonding pad.

First claim

What is claimed is:

1. An electronic device, comprising:
a first electronic unit and a second electronic unit;
a bonding pad disposed between the first electronic unit and the second electronic unit, wherein the bonding pad comprises a plurality of bonding pad regions which are not connected to each other;
an insulating layer disposed corresponding to the first electronic unit, to the second electronic unit and to the bonding pad; and
a circuit layer;
wherein, the first electronic unit is electrically connected to the second electronic unit through the circuit layer and through the bonding pad.

2. The electronic device of claim 1 , wherein the bonding pad further comprises:
a base layer; and
a conductor layer disposed corresponding to the base layer.

3. The electronic device of claim 2 , wherein the circuit layer comprises a first conductive layer in contact with at least a part of a surface of the first electronic unit, with at least a part of a surface of the insulating layer and with at least a part of a surface of the conductor layer.

4. The electronic device of claim 3 , wherein the circuit layer comprises a second conductive layer in contact with at least a part of a surface of the second electronic unit, with at least another part of the surface of the insulating layer and with at least another part of the surface of the conductor layer.

5. The electronic device of claim 2 , wherein the base layer comprises at least one rounded corner.

6. The electronic device of claim 1 , wherein the circuit layer comprises a first conductive layer and a second conductive layer, a space between the first conductive layer and the second conductive layer is d, a maximum width of one of the first conductive layer and the second conductive layers is W, and d≥(W/2).

7. The electronic device of claim 1 , wherein a maximum thickness of one of the first electronic unit and the second electronic unit is T1, a thickness of the bonding pad is T2, and T1≥T2.

8. The electronic device of claim 1 , wherein the insulating layer comprises a first portion, a second portion and a third portion, the first portion corresponds to the first electronic unit, the second portion corresponds to the second electronic unit, and the third portion corresponds to the bonding pad, a height of the third portion is H1, a maximum height of one of the first portion and the second portion is H2, and 0.9≤(H1/H2)≤1.1.

9. The electronic device of claim 1 , wherein in a top view of the electronic device, an angle θ is between an extension direction of the bonding pad and an extension direction of an edge of the first electronic unit close to the bonding pad, and 0≤θ<45°.

10. A method of forming an electronic device, comprising:
providing a substrate comprising a bonding pad, a first electronic unit and a second electronic unit;
dividing the bonding pad by laser to form a plurality of bonding pad regions; and
providing an insulating layer on the substrate, wherein the insulating layer is correspondingly provided with respect to the bonding pad, to the first electronic unit and to the second electronic unit;
wherein, the bonding pad is disposed between the first electronic unit and the second electronic unit, and the bonding pad is electrically connected to the first electronic unit and to the second electronic unit.

11. The method of forming the electronic device of claim 10 , wherein the bonding pad is provided on the substrate before the first electronic unit and the second electronic unit are provided on the substrate.

12. The method of forming the electronic device of claim 10 , wherein the first electronic unit and the second electronic unit are provided on the substrate before the bonding pad is provided on the substrate.

13. The method of forming the electronic device of claim 10 , wherein an extension direction of the bonding pad and an extension direction of a side of the first electronic unit close to the bonding pad have an angle θ, and 0≤θ<45°.

14. The method of forming the electronic device of claim 10 , further comprising:
providing a circuit layer on the insulating layer, and the first electronic unit is electrically connected to the second electronic unit through the circuit layer and through the bonding pad.

15. The method of forming the electronic device of claim 14 , wherein the circuit layer comprises a first conductive layer in contact with at least a part of a surface of the first electronic unit, with at least a part of a surface of the insulating layer and with at least a part of a surface of a conductor layer included in the bonding pad.

16. The method of forming the electronic device of claim 14 , wherein the circuit layer comprises a first conductive layer and a second conductive layer, a space between the first conductive layer and the second conductive layer is d, a maximum width of one of the first conductive layer and the second conductive layers is W, and d≥(W/2).

17. The method of forming the electronic device of claim 10 , wherein a maximum thickness of one of the first electronic unit and the second electronic unit is T1, a thickness of the bonding pad is T2, and T1≥T2.

18. The method of forming the electronic device of claim 10 , wherein the insulating layer comprises a first portion, a second portion and a third portion, the first portion corresponds to the first electronic unit, the second portion corresponds to the second electronic unit, and the third portion corresponds to the bonding pad, a height of the third portion is H1, a maximum height of one of the first portion and the second portion is H2, and 0.9≤(H1/H2)≤1.1.

Assignees

• Innolux Corp

Inventors

• Wang Cheng-Chi
• Ho Cheng-Hsien
• Yeh Kuo-Sheng
• Yueh Jui-Jen

Classifications

• H10W72/20

  Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title