Semiconductor chip having a crack stop structure

Patent metadata

Field	Value
Publication number	US-12406940-B2
Application number	US-202217582285-A
Country	US
Kind code	B2
Filing date	Jan 24, 2022
Priority date	Feb 23, 2021
Publication date	Sep 2, 2025
Grant date	Sep 2, 2025

Abstract

A semiconductor chip having a crack stop structure is disclosed. The crack stop structure includes one or more recesses formed in the semiconductor chip. The one or more recesses extend adjacent to and along a periphery of the semiconductor chip. The one or more recesses are filled with a metal material. The metal material has an intrinsic tensile stress at room temperature that induces compressive stress in at least a region of the periphery of the semiconductor chip.

First claim

What is claimed is:

1. A semiconductor chip comprising a crack stop structure, the crack stop structure comprising one or more recesses formed in the semiconductor chip, the one or more recesses extending adjacent to and along a periphery of the semiconductor chip, wherein:
the one or more recesses are filled with a metal material;
the metal material has an intrinsic tensile stress at room temperature to induce compressive stress in at least a region of the periphery of the semiconductor chip; and
a distance between the periphery of the semiconductor chip and the crack stop structure is equal to or less than 25 μm.

2. The semiconductor chip of claim 1 , wherein the intrinsic tensile stress at room temperature is equal to or greater than 200 MPa.

3. The semiconductor chip of claim 1 , wherein an entirety of the periphery of the semiconductor chip is biased in a state of the compressive stress induced by the crack stop structure.

4. The semiconductor chip of claim 1 , wherein the compressive stress at the region of the periphery or an entirety of the periphery of the semiconductor chip is equal to or less than −25 MPa.

5. The semiconductor chip of claim 1 , wherein the metal material comprises tungsten or tungsten titanium alloy or nickel or nickel vanadium alloy.

6. The semiconductor chip of claim 1 , wherein the metal material provides for a full material fill of the one or more recesses.

7. The semiconductor chip of claim 1 , wherein the semiconductor chip comprises a semiconductor substrate and a layer stack of insulating layers and metal layers disposed over the semiconductor substrate, and wherein at least some of the one or more recesses pass through the layer stack and extend into the substrate.

8. The semiconductor chip of claim 7 , wherein the at least some of the one or more recesses pass through the substrate.

9. The semiconductor chip of claim 1 , wherein the one or more recesses are formed as circumferential trenches.

10. The semiconductor chip of claim 1 , wherein the one or more recesses are formed as holes.

11. The semiconductor chip of claim 10 , wherein the holes are arranged as a first row and a second row of holes, and wherein a distance between the first row and the second row of holes is equal or less than 7 μm.

12. The semiconductor chip of claim 11 , wherein the holes of the first row and the second row are arranged in an interdigitated pattern such that a hole of the first row is opposite to a space between two holes of the second row and vice-versa.

13. A semiconductor chip comprising a crack stop structure, the crack stop structure comprising one or more recesses formed in the semiconductor chip, the one or more recesses extending adjacent to and along a periphery of the semiconductor chip, wherein:
the one or more recesses are filled with a metal material;
the metal material has an intrinsic tensile stress at room temperature to induce compressive stress in at least a region of the periphery of the semiconductor chip;
the crack stop structure is located outside an electrically active area of the semiconductor chip in an edge zone of the semiconductor chip; and
a distance between the periphery and the electrically active area is 15 μm or less.

Assignees

• Infineon Technologies Ag

Inventors

• Ananiev Sergey
• Bauer Andreas
• Goroll Michael
• Heidenblut Maria
• Kaiser Stefan
• Mackh Gunther
• Mutamba Kabula
• Pufall Reinhard
• Reuther Georg

Classifications

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10W42/00 Primary

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H01L23/562 Primary

  Electricity · mapped topic