Dynamic timing loop gain to compensate phase interpolation nonlinearities

Patent metadata

Field	Value
Publication number	US-12401488-B1
Application number	US-202418641575-A
Country	US
Kind code	B1
Filing date	Apr 22, 2024
Priority date	Mar 28, 2024
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

Integrated circuit transceivers having digital timing recovery loops with phase interpolation may incorporate dynamic loop gains to compensate for nonlinearities of the phase interpolation. An illustrative receiver circuit includes: a phase interpolator, a sampling element, a timing error estimator, and a feedback circuit. The phase interpolator provides a sampling signal by applying a phase shift to a clock signal in response to a phase control signal. The sampling element produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal. The timing error estimator produces a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal. The feedback circuit derives the phase control signal from the timing error signal using a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

First claim

What is claimed is:

1. An integrated receiver circuit that comprises:
a phase interpolator configured to provide a sampling signal by applying a phase shift to a clock signal in response to a phase control signal;
a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with the sampling signal;
a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; and
a feedback circuit configured to derive the phase control signal from the timing error signal, the feedback circuit including a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

2. The integrated receiver circuit of claim 1 , further comprising a demodulator that extracts a digital symbol stream from the digital receive signal.

3. The integrated receiver circuit of claim 1 , further comprising a histogram circuit configured to determine a relative probability of each phase control signal value.

4. The integrated receiver circuit of claim 3 , further comprising an inversion element configured to determine the scale factor using a reciprocal of said relative probability.

5. The integrated receiver circuit of claim 1 , wherein the scale factor is stored in a lookup table that is configured to receive the phase control signal.

6. The integrated receiver circuit of claim 1 , wherein the scale factor is derived from contents of a lookup table that is configured to receive the phase control signal.

7. The integrated receiver circuit of claim 1 , wherein the scaling element is part of a first feedback path in the feedback circuit configured to minimize a phase component of the estimated timing error, the feedback circuit further including a second feedback path configured to minimize a frequency component of the estimated timing error.

8. The integrated receiver circuit of claim 1 , further comprising a fractional-N phase lock loop configured to generate the clock signal, wherein the scaling element is part of a first feedback path in the feedback circuit configured to minimize a phase component of the estimated timing error, the feedback circuit further including an additional feedback path configured to derive a division-ratio error from the estimated timing error.

9. A clock recovery method that comprises, in an integrated receiver circuit:
providing a phase control signal to a phase interpolator to derive a sampling signal from a clock signal;
sampling an analog receive signal in accordance with the sampling signal to obtain a digital receive signal;
producing a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; and
deriving the phase control signal from the estimated timing error, said deriving including scaling the estimated timing error by a scale factor that depends on the phase control signal.

10. The clock recovery method of claim 9 , further comprising demodulating the digital receive signal to extract a digital symbol stream.

11. The clock recovery method of claim 9 , further comprising determining a relative probability of each phase control signal value.

12. The clock recovery method of claim 11 , further comprising determining the scale factor using a reciprocal of said relative probability.

13. The clock recovery method of claim 9 , wherein the phase control signal is used to retrieve the scale factor from a lookup table.

14. The clock recovery method of claim 9 , wherein the phase control signal is used to retrieve a relative probability from a lookup table, and wherein the method further includes deriving the scale factor from the relative probability.

15. The clock recovery method of claim 9 , wherein said scaling is performed in a first feedback path to minimize a phase component of the estimated timing error, and wherein said deriving the phase control signal employs a second feedback path to minimize a frequency component of the estimated timing error.

16. The clock recovery method of claim 9 , wherein said scaling is performed in a first feedback path to minimize a phase component of the estimated timing error, and wherein said method further includes providing a division-ratio error to a fractional-N phase lock loop that provides the clock signal, the division-ratio error being derived from the estimated timing error.

17. A nontransient information storage medium having a semiconductor intellectual property core to generate circuitry comprising:
a phase interpolator configured to provide a sampling signal by applying a phase shift to a clock signal in response to a phase control signal;
a sampling element configured to produce a digital receive signal by sampling an analog receive signal in accordance with the sampling signal;
a timing error estimator configured to produce a timing error signal indicating an estimated timing error of the sampling signal relative to the analog receive signal; and
a feedback circuit configured to derive the phase control signal from the timing error signal, the feedback circuit including a scaling element configured to scale the estimated timing error by a scale factor that depends on the phase control signal.

18. The nontransient information storage medium of claim 17 , wherein the circuitry further comprises a histogram circuit configured to determine a relative probability of each phase control signal value.

19. The nontransient information storage medium of claim 18 , wherein the circuitry further comprises an inversion element configured to determine the scale factor using a reciprocal of said relative probability.

20. The nontransient information storage medium of claim 17 , wherein the circuitry further comprises a lookup table configured to retrieve the scale factor in response to the phase control signal.

Assignees

• Credo Tech Group Ltd

Inventors

• Cai Fang
• Chang Xin
• Sun Junqing
• Qian Haoli

Classifications

• H04B1/16

  Circuits · CPC title

• H04B1/12

  Neutralising, balancing, or compensation arrangements · CPC title

• H04B1/40 Primary

  Circuits · CPC title

• H03L7/1976

  using a phase accumulator for controlling the counter or frequency divider · CPC title

• H04L7/0062

  detection of error based on data decision error, e.g. Mueller type detection · CPC title