Semiconductor package including electromagnetic shield structure

Patent metadata

Field	Value
Publication number	US-12400970-B2
Application number	US-202217745601-A
Country	US
Kind code	B2
Filing date	May 16, 2022
Priority date	Oct 12, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A semiconductor package includes; a package substrate, a semiconductor chip on the package substrate, an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, and a sealing member contacting the semiconductor chip and the electromagnetic shield structure, wherein the side cover includes first through holes and the upper cover includes second through holes.

First claim

What is claimed is:

1. A semiconductor package comprising:
a package substrate including a substrate pad, the substrate pad configured to be electrically grounded;
a semiconductor chip on the package substrate;
an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip; and
a sealing member comprising an insulating material contacting the semiconductor chip and the electromagnetic shield structure,
wherein the side cover has first through holes extending laterally through the side cover,
wherein the upper cover has second through holes extending vertically through the upper cover,
wherein the electromagnetic shield structure is electrically connected the substrate pad, and
wherein the sealing member extends into the first through holes and the second through holes.

2. The semiconductor package of claim 1 , wherein the sealing member includes an outer portion covering outer surfaces of the electromagnetic shield structure, an inner portion between inner surfaces of the electromagnetic shield structure and the semiconductor chip, first hole fillings filling the first through holes, and second hole fillings filling the second through holes.

3. The semiconductor package of claim 2 , wherein the inner portion, the outer portion, the first hole fillings, and the second hole fillings include a same material.

4. The semiconductor package of claim 2 , wherein the sealing member includes an epoxy molding compound.

5. The semiconductor package of claim 1 , wherein a thickness of the upper cover and a thickness of the side cover range between about 200 μm to about 1,000 μm.

6. The semiconductor package of claim 1 , wherein the sealing member includes a filler having a particle size, and a first size of the first through holes and a second size of the second through holes are at least twice the particle size of the filler.

7. The semiconductor package of claim 1 , wherein the semiconductor chip is configured to radiate electromagnetic energy at a first wavelength λ of a maximum operation frequency, and a first size of the first through holes and a second size of the second through holes are each less than or equal to λ/50.

8. The semiconductor package of claim 1 , wherein a first size of the first through holes and a second size of the second through holes each range between about 0.11 mm to about 1.03 mm.

9. The semiconductor package of claim 1 , further comprising:
first upper substrate pads connecting the semiconductor chip to an internal interconnection pattern within the package substrate; and
wherein the substrate pad includes a second upper substrate pad configured to physically connect the electromagnetic shield structure.

10. The semiconductor package of claim 9 , further comprising:
a conductive bonding material layer between the second upper substrate pad and the electromagnetic shield structure.

11. The semiconductor package of claim 9 , further comprising:
chip connecting bumps between the first upper substrate pads and the semiconductor chip, wherein the sealing member fills a gap between the semiconductor chip and the package substrate and surrounds the chip connecting bumps.

12. The semiconductor package of claim 1 , further comprising:
chip connecting bumps between first upper substrate pads on an upper surface of the package substrate and the semiconductor chip; and
an underfill material layer filling a gap between the semiconductor chip and the upper surface of the package substrate and surrounding the chip connecting bumps.

13. The semiconductor package of claim 1 , wherein the side cover includes a first side shielding layer of a first material type and a second side shielding layer of a second material type different from the first material type, the second side shielding layer being stacked on the first side shielding layer, and
the upper cover includes a first upper shielding layer of a third material type and a second upper shielding layer of a fourth material type different from the third material type, the second upper shielding layer being stacked on the first upper shielding layer.

14. The semiconductor package of claim 1 , further comprising:
an antenna pattern between the semiconductor chip and the side cover, electrically connected to the semiconductor chip, and configured to communicate radio frequency signals.

15. The semiconductor package of claim 1 , wherein the side cover has a rectangular ring-like shape including four segments, and the first through holes penetrate each of the four segments.

16. A semiconductor package comprising:
a package substrate including a base, first upper substrate pads on an upper surface of the package substrate, a second upper substrate pad on the upper surface of the package substrate, and an internal interconnection pattern within the base and connected to the first upper substrate pads;
a semiconductor chip including chip connecting bumps respectively connected to the first upper substrate pads;
an electromagnetic shield structure on the package substrate and including an upper cover covering an upper surface of the semiconductor chip and a side cover surrounding the semiconductor chip, wherein the side cover is electrically connected to the second upper substrate pad and ground; and
a sealing member comprising an insulating material between the semiconductor chip and the electromagnetic shield structure,
wherein the side cover has first through holes extending in a first direction through the side cover,
the upper cover has second through holes extending in a second direction through the upper cover,
the second direction is different from the first direction, and
the sealing member extends into the first through holes and the second through holes.

17. The semiconductor package of claim 16 , wherein the sealing member includes a filler having a particle size, and a first size of the first through holes is at least twice that of the particle size,
wherein the first direction is a horizontal direction, and
wherein the second direction is a vertical direction.

18. A semiconductor package comprising:
a package substrate including first upper substrate pads on an upper surface of the package substrate and a second upper substrate pad connected to ground and on the upper surface of the package substrate;
a radio frequency integrated circuit mounted on the package substrate using chip connecting bumps respectively connected to the first upper substrate pads, wherein the radio frequency integrated circuit is configured to communicate a radio frequency signal having a wavelength λ;
an electromagnetic shield structure mounted on the package substrate and including an upper cover covering an upper surface of the radio frequency integrated circuit and a side cover surrounding side surfaces of the radio frequency integrated circuit, wherein the side cover is penetrated by regularly spaced first through holes and the upper cover is penetrated by regularly spaced second through holes; and
a sealing member comprising an insulating material disposed between the electromagnetic shield structure and the radio frequency integrated circuit, surrounding the chip connecting bumps, and including a filler having a particle size and filling the first through holes and the second through holes,
wherein a thickness of the upper cover and a thickness of the side cover range between about 200 μm to about 1,000 μm, a first size of the first through holes and a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jongwan
• Lee Yongkwan
• Koh Kyonghwan
• Kim Seunghwan
• Kim Jungjoo
• Park Junwoo
• Jeon Taejun

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/203

  Electrical connections · CPC title