MEMS microphone structure and method of manufacturing the same

US9681234B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9681234-B2
Application numberUS-201314889433-A
CountryUS
Kind codeB2
Filing dateDec 10, 2013
Priority dateMay 9, 2013
Publication dateJun 13, 2017
Grant dateJun 13, 2017

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A MEMS microphone structure, comprising a semiconductor substrate having a cavity, a first dielectric layer having a through-hole communicating with the cavity, a lower diaphragm electrode formed above the through-hole and at least partially attached to the upper surface of the first dielectric layer, and an upper electrode structure with an insulating layer. The upper electrode structure comprises an annular supporter, a back plate having multiple holes, and an upper electrode connection. At least a part of the annular supporter extends downwardly to the lower diaphragm electrode while the rest of the annular supporter extends downwardly to the substrate. The back plate is suspended above the lower diaphragm electrode by the annular supporter, forming an air gap therebetween. An upper electrode is embedded in the insulating layer at the back plate and is lead out by the upper electrode connection.

First claim

Opening claim text (preview).

The invention claimed is: 1. A MEMS microphone structure comprising: a semiconductor substrate having a cavity therein; a first dielectric layer formed on the semiconductor substrate having a through-hole communicating with the cavity; a lower diaphragm electrode formed above the through-hole and at least partially attached to an upper surface of the first dielectric layer, wherein the lower diaphragm electrode is lead out through a lower electrode connection; and an upper electrode structure with an insulating layer, wherein the upper electrode structure comprises an annular supporter, a back plate having multiple holes, and an upper electrode connection; wherein at least a part of the annular supporter extends downwardly to the lower diaphragm electrode while the rest of the annular supporter extends downwardly to the semiconductor substrate; the back plate is suspended above the lower diaphragm electrode by the annular supporter, forming an air gap therebetween; an upper electrode is embedded in the insulating layer at the back plate and is lead out by the upper electrode connection; wherein the annular supporter is an annular trench; the annular trench comprises a first portion formed outside the lower diaphragm electrode, the bottom of which extending to the semiconductor substrate; the insulating layer includes a first opening at the upper electrode connection; the upper electrode in the insulating layer at the back plate is continuously distributed and embedded in the insulating layer at the first portion of the annular trench and in the insulating layer at the upper electrode connection, and is exposed at the first opening. 2. The MEMS microphone structure according to claim 1 , wherein the annular trench comprises a second portion, the bottom of which extending to the lower diaphragm electrode. 3. The MEMS microphone structure according to claim 2 , wherein the lower electrode connection comprises a contact hole that is extended to and connected with the lower diaphragm electrode, the contact hole is filled with a lower electrode lead to lead out the lower diaphragm electrode; the insulating layer at the second portion of the annular trench extends to cover the lower electrode lead and forms a second opening to partially expose the lower electrode lead. 4. The MEMS microphone structure according to claim 1 , wherein the upper electrode is completely enclosed by the insulating layer at the back plate. 5. The MEMS microphone structure according to claim 1 , wherein the annular supporter is arranged concentric with the cavity. 6. The MEMS microphone structure according to claim 1 , wherein the insulating layer at the back plate comprises downward-extended protrusions formed on the surface facing the lower diaphragm electrode, wherein each of the protrusions has a thickness ranges from 0.3 um to 1 um. 7. The MEMS microphone structure according to claim 3 , wherein the lower diaphragm electrode and the upper electrode are conductive thin films, the conductive thin films are metal thin films, or doped polysilicon thin films, or amorphous silicon thin films; wherein the material of the insulating layer is silicon nitride. 8. The MEMS microphone structure according to claim 3 , wherein the upper electrode and the lower electrode lead are metal thin films made of the same material. 9. The MEMS microphone structure according to claim 1 , wherein the lower diaphragm electrode has a circular shape with a diameter ranging from 200 um to 2 mm; the thickness of the lower diaphragm electrode ranges from 4000 Å to 3 um; the upper electrode embedded in the back plate has a circular shape with a diameter ranging from 200 um to 2 mm; the thickness of the lower diaphragm electrode ranges from 4000 Å to 10 um; the cavity has a shape of cylinder or cone with a diameter at the top ranging from 200 um to 1 mm and a depth ranging from 200 um to 700 um. 10. A method of manufacturing a MEMS microphone structure comprising the following steps: forming a first dielectric layer, a lower diaphragm electrode and a second dielectric layer successively on a substrate; performing lithography and etching processes to form an annular trench, at least a part of the bottom of which extending to the lower diaphragm electrode while the rest of the bottom of which extending to the substrate, wherein an area enclosed by an inner sidewall of the annular trench forms a back plate region; depositing a first insulating layer, wherein the first insulating layer filled in the annular trench forms an annular supporter; depositing an upper electrode and patterning to form a patterned upper electrode covering at least a part of the first insulating layer within the back plate region; depositing a second insulating layer; forming an upper electrode connection and a lower electrode connection; etching to form multiple holes penetrating the first insulating layer and the second insulating layer within the back plate region to form a back plate; forming a cavity extending through the substrate, the top of which is within the area enclosed by the inner sidewall of the annular trench; and performing releasing process to remove the first dielectric layer and the second dielectric layer within the back plate region and above the cavity together, so as to form an air gap between the back plate and the lower diaphragm electrode. 11. The method according to claim 10 , wherein the annular trench comprises a first portion formed outside the lower diaphragm electrode, the bottom of which extending to the semiconductor substrate, and a second portion, the bottom of which extending to the lower diaphragm electrode. 12. The method according to claim 11 , wherein the patterned upper electrode is arranged continuously on the first insulating layer at the back plate region and the first insulating layer within the first portion of the annular trench, and is coated by the second insulating layer. 13. The method according to claim 12 , wherein the step of forming the upper electrode connection comprises forming a first opening in the second insulating layer to expose the upper electrode filled in the first portion of the annular trench, so as to form the upper electrode connection at the first opening. 14. The method according to claim 10 , wherein after the step of depositing the first insulating layer, the method further comprises: etching the first insulating layer and the second insulating layer at areas outside an outer periphery of the annular trench to form a contact hole the bottom of which extending to the lower diaphragm electrode; wherein the upper electrode is filled in the contact hole to be connected to the lower diaphragm electrode, and is coated by the second insulating layer; wherein the step of forming the lower electrode connection comprises forming a second opening in the second insulating layer to expose the upper electrode filled in the contact hole, so as to form the lower electrode connection at the second opening. 15. The method according to claim 10 , wherein the step of depositing the upper electrode on the first insulating layer and patterning comprises etching to form multiple apertures in the upper electrode at the back plate region; wherein the second insulating layer is connected with the first insulating layer by filling the apertures; wherein the step of etching to form multiple holes penetrating the first insulating layer and the second insulating layer within the back plate region to form the back plate further comprises etching connecting portions of the first and second insulating layers to form the holes such that the upper electrode at the bac

Assignees

Inventors

Classifications

  • Microphones or microspeakers · CPC title

  • H04R19/04Primary

    Microphones (H04R19/01 takes precedence) · CPC title

  • Enhancing the perception of the sound image or of the spatial distribution using head related transfer functions [HRTF's] or equivalents thereof, e.g. interaural time difference [ITD] or interaural level difference [ILD] · CPC title

  • Indicating arrangements; Control arrangements, e.g. balance control · CPC title

  • Avoid or control under-cutting · CPC title

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What does patent US9681234B2 cover?
A MEMS microphone structure, comprising a semiconductor substrate having a cavity, a first dielectric layer having a through-hole communicating with the cavity, a lower diaphragm electrode formed above the through-hole and at least partially attached to the upper surface of the first dielectric layer, and an upper electrode structure with an insulating layer. The upper electrode structure compr…
Who is the assignee on this patent?
Shanghai Ic R&D Ct Co Ltd, Shanghai Ic R&D Ct Co Ltd
What technology area does this patent fall under?
Primary CPC classification H04R19/04. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 13 2017 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).