Display apparatus having signal lines on a multi-layer metal layer

Patent metadata

Field	Value
Publication number	US-12400599-B2
Application number	US-202218266612-A
Country	US
Kind code	B2
Filing date	Mar 8, 2022
Priority date	Mar 8, 2022
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

The present disclosure provides a display apparatus, a display panel and a preparation method. The display panel includes a base substrate, a driving circuit provided on a side of the base substrate and a multi-layer metal layer: the base substrate includes a display region and a peripheral region located on a periphery of the display region; the driving circuit includes a peripheral circuit and a pixel circuit, the peripheral circuit is located at the peripheral region, the pixel circuit is located at the display region, and the peripheral circuit is connected with the pixel circuit and configured to provide a driving signal to the pixel circuit; the peripheral circuit includes a plurality of signal lines distributed in at least two metal layers.

First claim

What is claimed is:

1. A display panel, comprising a base substrate, a driving circuit provided on a side of the base substrate and a multi-layer metal layer;
wherein the base substrate comprises a display region and a peripheral region located at a periphery of the display region;
the driving circuit comprises a peripheral circuit and a pixel circuit, the peripheral circuit is located at the peripheral region, the pixel circuit is located at the display region, and the peripheral circuit is connected with the pixel circuit and configured to provide a driving signal to the pixel circuit;
the peripheral circuit comprises a plurality of signal lines distributed in at least two layers of the multi-layer metal layer;
wherein the multi-layer metal layer comprises a first metal layer and a second metal layer arranged in sequence along a direction away from the base substrate, and the plurality of signal lines comprise a clock signal line and a voltage signal line;
wherein the peripheral circuit comprises a gate driving circuit, the gate driving circuit comprises a plurality of first shift register units in a cascade connection and the plurality of signal lines, and the first shift register unit comprises a transistor;
the clock signal line is configured to transmit a clock signal to the first shift register unit, and the voltage signal line is configured to transmit a voltage signal to the first shift register unit;
the first metal layer comprises a source and a drain of the transistor in the first shift register unit;
the second metal layer is provided on a side of the first shift register unit away from the base substrate;
an orthographic projection of the signal line, distributed in the second metal layer, in the gate driving circuit on the base substrate at least partially overlaps with an orthographic projection of the first shift register unit on the base substrate.

2. The display panel according to claim 1 , wherein the peripheral circuit comprises a light-emitting control circuit, and the light-emitting control circuit comprises the plurality of signal lines;
at least one of the plurality of signal lines of the gate driving circuit or the plurality of signal lines of the light-emitting control circuit are distributed in at least two layers of the multi-layer metal layer.

3. The display panel according to claim 2 , wherein among the plurality of signal lines, a part of the signal lines are distributed in the first metal layer, and a part of the signal lines are distributed in the second metal layer.

4. The display panel according to claim 3 , wherein the peripheral circuit comprises the light-emitting control circuit, the light-emitting control circuit comprises a plurality of second shift register units in a cascade connection and the plurality of signal lines, and the second shift register unit comprises a transistor;
the clock signal line is configured to transmit a clock signal to the second shift register unit, and the voltage signal line is configured to transmit a voltage signal to the second shift register unit;
the first metal layer comprises a source and a drain of the transistor in the second shift register unit;
the second metal layer is provided on a side of the second shift register unit away from the base substrate;
an orthographic projection of the signal line, distributed in the second metal layer, in the light-emitting control circuit on the base substrate at least partially overlaps with an orthographic projection of the second shift register unit on the base substrate.

5. The display panel according to claim 4 , further comprising:
a cathode signal line, provided on a side of the base substrate and located at the peripheral region, wherein the cathode signal line is distributed in the first metal layer,
a cathode lapping line with an end lapping the cathode signal line, wherein at least a part of the cathode lapping line is distributed in the second metal layer.

6. The display panel according to claim 5 , wherein the cathode signal line is provided on a side of the light-emitting control circuit away from the display region;
an orthographic projection of the cathode lapping line on the base substrate at least partially overlaps with the orthographic projection of the second shift register unit on the base substrate.

7. The display panel according to claim 1 , further comprising an initial signal line, the initial signal line located at the peripheral region and configured to transmit an initial signal to the pixel circuit, wherein the initial signal line is distributed in the second metal layer.

8. The display panel according to claim 7 , wherein an orthographic projection of the initial signal line on the base substrate at least partially overlaps with the orthographic projection of the first shift register unit on the base substrate.

9. The display panel according to claim 8 , wherein the gate driving circuit comprises a first gate driving circuit and a second gate driving circuit, the first shift register unit comprises a first sub-shift register unit and a second sub-shift register unit, the first gate driving circuit comprises the first sub-shift register unit, and the second gate driving circuit comprises the second sub-shift register unit, the second gate driving circuit is located on a side of the first gate driving circuit close to the display region;
the orthographic projection of the initial signal line on the base substrate at least partially overlaps with an orthographic projection of the second sub-shift register unit on the base substrate.

10. The display panel according to claim 9 , wherein the pixel circuit comprises a low temperature polysilicon transistor and an oxide transistor;
the first gate driving circuit is configured to drive the oxide transistor, and the second gate driving circuit is configured to drive the low temperature polysilicon transistor.

11. The display panel according to claim 9 , further comprising:
a planarization layer, provided between the first metal layer and the second metal layer, wherein an orthographic projection of the planarization layer on the base substrate covers a gap between orthographic projections of the first sub-shift register unit and the second sub-shift register unit on the base substrate.

12. The display panel according to claim 7 , further comprising an electrical connection line, wherein the peripheral circuit is connected with the pixel circuit through the electrical connection line;
the initial signal line is provided on a side of the electrical connection line away from the base substrate;
an orthographic projection of the initial signal line on the base substrate at least partially overlaps with an orthographic projection of the electrical connection line on the base substrate.

13. The display panel according to claim 1 , further comprising:
an encapsulation layer, provided on sides of the driving circuit and the multi-layer metal layer away from the base substrate;
wherein the encapsulation layer comprises a first inorganic layer and a second inorganic layer arranged in sequence along a direction away from the base substrate, an orthographic projection of the second inorganic layer on the base substrate covers an orthographic projection of the first inorganic layer on the base substrate, and an area of the orthographic projection of the second inorganic layer on the base substrate is greater than an area of the orthographic projection of the first inorganic layer on the base substrate.

14. The display panel according to claim 13 , wherein the first inorganic layer is provided with a first surface away from the base subst

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Song Erlong
• Yan Hailong
• Zhang Jingli
• Gao Yagui
• Zhang Kai
• Cheng Rui
• Shi Kunyan
• Chen Yafei

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title