Flat display device having a plurality of link lines and method of fabricating the same

US9274389B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9274389-B2
Application numberUS-201113330328-A
CountryUS
Kind codeB2
Filing dateDec 19, 2011
Priority dateJun 10, 2011
Publication dateMar 1, 2016
Grant dateMar 1, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a flat display device and method of fabricating the same which can make narrow bezel design easy and minimize resistance variation between adjacent link lines for improving of a picture quality. The flat display device includes a display region having a plurality of pixels, a driving integrated circuit for forwarding driving signals for driving the plurality of pixels, and a plurality of link lines for transmitting the driving signals to the display region, wherein each of the plurality of link lines includes a first metal line, a second metal line formed on a layer different from the first metal line, and a contact portion for connecting the first and second metal lines to each other.

First claim

Opening claim text (preview).

What is claimed is: 1. A flat display device comprising: a display region including left and right vertical sides, and top and bottom horizontal sides, and having a plurality of gate lines and a plurality of data lines; a driving integrated circuit for supplying driving signals for driving a plurality of pixels; and a plurality of link lines for transmitting the driving signals to the display region, the plurality of link lines having at least a first link line and a second link line adjacent to the first link line, wherein the first link line is positioned outside of the second link line with respect to the display region, wherein the first link line includes: a first metal line connected to the driving integrated circuit, a second metal line connected to the display region and formed on a layer different from the first metal line, and a first contact portion for connecting the first and second metal lines to each other, wherein the second link line includes: a third metal line connected to the driving integrated circuit, a fourth metal line connected to the display region and formed on a layer different from the third metal line, a second contact portion for connecting the third and fourth metal lines to each other, and wherein the first metal line is formed on the same layer as the fourth metal line, and the second metal line is formed on the same layer as the third metal line, wherein the first metal line has a length that is greater than a length of the third metal line, the fourth metal line has a length that is greater than a length of the second metal line, and the first contact portion is separated from the driving IC by a first distance that is larger than a second distance separating the second contact portion from the driving IC, wherein a vertical portion of the second metal line is directly connected to the first contact portion and parallel to the left vertical side of the display region, and a horizontal portion of the second metal line is connected to the first contact portion via a corner having a 90 degree angle and perpendicular to the left vertical side, the vertical portion of the second metal line being longer than the horizontal portion of the second metal line, and wherein a vertical portion of the fourth metal line is directly connected to the second contact portion and parallel to the left vertical side of the display region, and a horizontal portion of the fourth metal line is connected to the second contact portion via a corner having a 90 degree angle and perpendicular to the left vertical side, the vertical portion of the fourth metal line being longer than the horizontal portion of the fourth metal line. 2. The flat display device as claimed in claim 1 , wherein, the resistances of the plurality of link lines are substantially the same as each other. 3. The flat display device as claimed in claim 2 , wherein, cross sectional areas of the plurality of link lines are formed to be gradually greater from the shortest link line to the longest link line. 4. The flat display device as claimed in claim 1 , wherein the plurality of link lines includes either or both of gate link lines for transmitting scan signal from the driving integrated circuit to gate lines in the display region and data link lines for transmitting data signal from the driving integrated circuit to data lines in the display region. 5. The flat display device as claimed in claim 1 , wherein, the first contact portion includes: a first metal pad which is an extension from the first metal line; a gate insulating layer formed to cover the first metal pad and the first metal line; a second metal pad which is an extension from the second metal line on the gate insulating layer; a protective layer formed on the gate insulating layer having the second metal pad and the second metal line; a first contact hole passing through the protective layer and the gate insulating layer to expose the first metal pad; a second contact hole passing through the protective layer to expose the second metal pad; and a contact electrode formed to cover the first contact hole and the second contact hole, to connect the first and second metal lines to each other. 6. The flat display device as claimed in claim 5 , wherein, the first contact portion further includes an etch stopper film between the gate insulating layer and the second metal pad. 7. The flat display device as claimed in claim 1 , wherein, the second contact portion includes: a fourth metal pad which is an extension from the fourth metal line; a gate insulating layer formed to cover the fourth metal pad and the fourth metal line; a third metal pad which is an extension from the third metal line on the gate insulating layer; a protective layer formed on the gate insulating layer having the third metal pad and the third metal line; a first contact hole passing through the protective layer and the gate insulating layer to expose the fourth metal pad; a second contact hole passing through the protective layer to expose the third metal pad; and a contact electrode formed to cover the first contact hole and the second contact hole, to connect the third and fourth metal lines to each other. 8. The flat display device as claimed in claim 7 , wherein, the second contact portion further includes an etch stopper film between the gate insulating layer and the third metal pad. 9. The flat display device as claimed in claim 1 , wherein the plurality of link lines are a plurality of gate link lines, respectively.

Assignees

Inventors

Classifications

  • Interconnections, e.g. scanning lines · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • G02F1/1345Primary

    Conductors connecting electrodes to cell terminals · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US9274389B2 cover?
The present invention relates to a flat display device and method of fabricating the same which can make narrow bezel design easy and minimize resistance variation between adjacent link lines for improving of a picture quality. The flat display device includes a display region having a plurality of pixels, a driving integrated circuit for forwarding driving signals for driving the plurality of …
Who is the assignee on this patent?
Kang Sung-Gu, Park Sung-Il, Lg Display Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/1345. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).