Display device and electronic device

Patent metadata

Field	Value
Publication number	US-12400569-B2
Application number	US-202218273095-A
Country	US
Kind code	B2
Filing date	Jan 17, 2022
Priority date	Jan 28, 2021
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

First claim

The invention claimed is:

1. A display device comprising:
a first layer;
a second layer positioned above the first layer; and
a third layer positioned above the second layer,
wherein the first layer comprises a driver circuit and a plurality of first wirings,
wherein the driver circuit comprises a plurality of output terminals positioned along a first direction,
wherein the plurality of output terminals are electrically connected to the plurality of first wirings,
wherein the plurality of first wirings are extended perpendicular to the first direction,
wherein the third layer comprises a pixel array and a plurality of second wirings,
wherein the pixel array comprises a plurality of pixel circuits arranged in a matrix,
wherein the plurality of pixel circuits are electrically connected to the plurality of second wirings,
wherein the plurality of second wirings are parallel to each other and extended in a column direction of the pixel array,
wherein the second layer comprises a plurality of first contact portions,
wherein the plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions, and
wherein the driver circuit is configured to control the plurality of pixel circuits.

2. The display device according to claim 1 ,
wherein one of the plurality of first contact portions is positioned inside the pixel array and inside or outside the plurality of pixel circuits in a top view.

3. The display device according to claim 1 ,
wherein the first layer comprises a semiconductor substrate comprising silicon and a plurality of second contact portions,
wherein the driver circuit comprises a plurality of transistors each including the silicon in a channel formation region,
wherein a plurality of low-resistance regions to be the plurality of first wirings are positioned on a top surface of the semiconductor substrate,
wherein the plurality of second contact portions are positioned between the plurality of first contact portions and the plurality of second contact portions, and
wherein the plurality of low-resistance regions comprise one of a source and a drain of each of the plurality of transistors.

4. The display device according to claim 1 ,
wherein the third layer comprises a plurality of third wirings positioned along a second direction,
wherein the plurality of third wirings are parallel to each other and extended in a row direction of the pixel array, and
wherein the plurality of first wirings extend in a third direction intersecting the first direction and the second direction.

Assignees

• Semiconductor Energy Lab

Inventors

• Kozuma Munehiro
• Onuki tatsuya
• Ikeda Takayuki
• Matsuzaki Takanori

Classifications

• H10K59/873

  Encapsulations · CPC title

• H10K59/8722

  Peripheral sealing arrangements, e.g. adhesives, sealants · CPC title

• H10K59/871

  Self-supporting sealing arrangements · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title