Inline data inspection for workload simplification

Patent metadata

Field	Value
Publication number	US-12399716-B2
Application number	US-202418625903-A
Country	US
Kind code	B2
Filing date	Apr 3, 2024
Priority date	Aug 31, 2017
Publication date	Aug 26, 2025
Grant date	Aug 26, 2025

Abstract

A method, computer readable medium, and processor are described herein for inline data inspection by using a decoder to decode a load instruction, including a signal to cause a circuit in a processor to indicate whether data loaded by a load instruction exceeds a threshold value. Moreover, an indication of whether data loaded by a load instruction exceeds a threshold value may be stored.

First claim

What is claimed is:

1. A processor, comprising:
a load/store circuit to load stored data indicated by a load instruction; and
an inspection circuit to indicate to the load/store circuit whether the stored data to be loaded by the load instruction equals zero.

2. The processor of claim 1 , wherein the inspection circuit is to transmit the stored data and a predicate value to the load/store circuit, wherein the predicate value is asserted when the stored data equals zero and is negated when the stored data does not equal zero.

3. The processor of claim 1 , wherein the load/store circuit is to store the stored data in a register specified by the load instruction.

4. The processor of claim 1 , wherein the load/store circuit is to discard the stored data based, at least in part, on a predicate signal.

5. The processor of claim 1 , wherein the stored data comprises two or more operands of an arithmetic operation.

6. The processor of claim 1 , wherein a branch instruction follows the load instruction in a sequence of instructions by the processor and a predicate signal controls execution of the branch instruction.

7. The processor of claim 1 , wherein a portion of instructions after the load instruction are not executed when the stored data equals zero.

8. A method, comprising:
using a load/store circuit to load stored data indicated by a load instruction; and
using an inspection circuit to indicate to the load/store circuit whether the stored data to be loaded by the load instruction equals zero.

9. The method of claim 8 , wherein decoding of the load instruction causes the inspection circuit to compare the stored data with zero.

10. The method of claim 8 , further comprising:
using a functional circuit to discard the stored data when the stored data equals zero.

11. The method of claim 8 , further comprising:
executing a second instruction that follows the load instruction in a sequence of instructions based at least in part on the indication by the inspection circuit.

12. The method of claim 8 , wherein the indication by the inspection circuit is through a signal used to calculate a predicate value.

13. The method of claim 8 , wherein a predicate value changes execution of one or more instructions after the load instruction, the predicate value is asserted when the stored data equals zero and is negated when the stored data does not equal zero.

14. The method of claim 8 , wherein the stored data is compared with a non-zero threshold value indicated by a second load instruction.

15. A system, comprising:
a load/store circuit to load stored data indicated by a load instruction; and
an inspection circuit to indicate to the load/store circuit whether the stored data to be loaded by the load instruction equals zero.

16. The system of claim 15 , wherein the inspection circuit is to transmit the stored data and a predicate value to the load/store circuit, wherein the predicate value is asserted when the stored data equals zero and is negated when the stored data does not equal zero.

17. The system of claim 15 , wherein the load/store circuit is to discard the stored data based, at least in part, on a predicate signal.

18. The system of claim 15 , wherein the stored data comprises one or more portions representing one or more values, wherein a predicate value is shared among the one or more values.

19. The system of claim 15 , wherein a branch instruction follows the load instruction in a sequence of instructions by the system and a predicate signal controls execution of the branch instruction.

20. The system of claim 15 , wherein the inspection circuit is to indicate to the load/store circuit whether the stored data to be loaded by the load instruction equals a threshold value determined by one or more neural networks.

Assignees

• Nvidia Corp

Inventors

• Pool Jeffrey Michael
• Kerr Andrew
• Tran John
• Siu Ming Y
• Oberman Stuart

Classifications

• G06F9/30021

  Compare instructions, e.g. Greater-Than, Equal-To, MINMAX · CPC title

• G06N20/00

  Machine learning · CPC title

• G06F9/30094

  Condition code generation, e.g. Carry, Zero flag · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title