Mechanism for performing speculative predicated instructions

Patent metadata

Field	Value
Publication number	US-9298456-B2
Application number	US-201213590870-A
Country	US
Kind code	B2
Filing date	Aug 21, 2012
Priority date	Aug 21, 2012
Publication date	Mar 29, 2016
Grant date	Mar 29, 2016

Abstract

A mechanism for executing speculative predicated instructions may include execution of initiating execution of a vector instruction when one or more operands upon which the vector instruction depends are available for use, even if a predicate vector that the vector instruction also depends is not available. If the predicate vector was not available, the results of the execution of the vector instruction may be temporarily held until the predicate vector becomes available, at which time, a destination vector may be updated with the results.

First claim

What is claimed is:

1. A functional unit, comprising:
a controller configured to initiate execution of a vector instruction in response to a determination that one or more operands on which the vector instruction depends are available for use; and
a holding unit configured to temporarily store results of the vector instruction;
wherein in response to receiving a determination that a predicate vector on which the vector instruction depends was not yet available for use upon initiation of the vector instruction, the controller is further configured to:
temporarily store results of the vector instruction within the holding unit, such that the results are not made available to one or more operations that depend upon the vector instruction; and
in response to receiving a determination that the predicate vector is available for use, update the temporarily stored results of the vector instruction dependent upon one or more element positions of the vector instruction that are indicated to be active by the predicate vector, and store the updated results in a destination register that is made available to the one or more operations that depend upon the vector instruction.

2. The functional unit of claim 1 , wherein in response to receiving the determination that the predicate vector was not yet available for use upon initiation of the vector instruction, the controller is further configured to suppress any faults raised during execution of the vector instruction.

3. The functional unit of claim 2 , wherein in response to a determination that one or more faults were raised during execution of the vector instruction, the controller is further configured to re-initiate the vector instruction after receiving the determination that the predicate vector is available for use.

4. The functional unit of claim 3 , wherein the controller is further configured to raise faults that correspond to active elements and which occur during the re-initiation of the vector instruction.

5. The functional unit of claim 2 , wherein the controller is further configured to hold the faults raised during execution of the vector instruction prior to the predicate vector being available for use, and to re-initiate the vector instruction after receiving the determination that the predicate vector is available for use only in response to determining, based upon the predicate vector, that the faults raised during execution of the vector instruction correspond to active elements of the vector instruction.

6. The functional unit of claim 1 , wherein the vector instruction comprises a vector load instruction, and the one or more operands comprise one or more memory addresses on which the vector load instruction depends.

7. A processor, comprising:
an execution unit configured to initiate generation of a predicate vector that includes one or more predicate elements; and
a functional unit configured to initiate execution of a vector instruction in response to a determination that one or more operands on which the vector instruction depends are available for use;
wherein in response to a determination that the predicate vector was not yet available upon initiation of the vector instruction, the functional unit is further configured to:
hold results of the vector instruction in abeyance until the predicate vector becomes available for use, such that the results are not made available to one or more operations that depend upon the vector instruction; and
in response to a determination that the predicate vector is available for use, update the results of the vector instruction dependent upon one or more element positions of the vector instruction that are indicated to be active by the predicate vector, and store the updated results to a destination that is made available to one or more operations that depend upon the vector instruction.

8. The processor of claim 7 , wherein to hold results of the vector read operation in abeyance, the functional unit is further configured to suppress any faults raised during execution of the vector instruction.

9. The processor of claim 8 , wherein in response to a determination that one or more faults were raised during execution of the vector instruction, the functional unit is further configured to re-initiate the vector instruction after the predicate vector becomes available for use.

10. The processor of claim 9 , wherein the functional unit is configured to raise faults that correspond to active elements and which occur during the re-initiation of the vector instruction.

11. The processor of claim 8 , wherein the functional unit is configured to hold the faults raised during execution of the vector instruction prior to the predicate vector being available for use, and in response to determining, based upon the predicate vector, that the faults raised during execution of the vector instruction correspond to active elements of the vector instruction, the functional unit is further configured to re-initiate execution of the vector instruction after receiving the determination that the predicate vector is available for use.

12. A method comprising:
initiating generation of a predicate vector including one or more elements;
prior to the predicate vector becoming available for use, initiating a vector instruction in response to a determination that one or more operands on which the vector instruction depends are available for use;
holding results of the vector instruction in abeyance until the predicate vector becomes available for use, such that the results are not made available to one or more operations that depend upon the vector instruction; and
in response to a determination that the predicate vector is available for use, updating the results of the vector instruction dependent upon one or more element positions of the vector instruction that are indicated to be active by the predicate vector, and storing the updated results to a destination that is made available to one or more operations that depend upon the vector instruction.

13. The method of claim 12 , further comprising, in response to detecting a fault during execution of the vector instruction, suppressing the fault, discarding the results of the vector instruction, and re-initiating the vector instruction after determining that the predicate vector is available.

14. The method of claim 13 , wherein re-initiating the vector instruction after determining that the predicate vector is available further comprises re-initiating the vector instruction only in response to determining, based upon the predicate vector, that the faults raised during execution of the vector instruction correspond to active elements of the vector instruction.

15. The method of claim 13 , further comprising raising faults that correspond to active elements and which occur during the re-initiation of the instruction.

16. The method of claim 12 , wherein each of the one or more elements of the predicate vector control whether a corresponding element in the destination will receive a result of the vector instruction or remain unmodified.

17. The method of claim 12 , wherein initiating generation of the predicate vector includes executing a predicate generating instruction.

18. The method of claim 17 , wherein the predicate generating instruction is a Macroscalar GeneratePredicates instruction.

19. A functional unit, comprising:
a controller configured to initiate execution of a vector instruction when one or more operands on which the vector instruction depends are available, and prior to a predicate vector on which th

Assignees

• Gonion Jeffry E
• Apple Inc

Inventors

• Gonion Jeffry E

Classifications

• G06F9/30036 Primary

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/30043

  LOAD or STORE instructions; Clear instruction · CPC title

• G06F9/3859

  Physics · mapped topic

• G06F9/3842

  Speculative instruction execution · CPC title