Zero operand instruction conversion for accelerating sparse computations in a central processing unit pipeline

Patent metadata

Field	Value
Publication number	US-11714652-B2
Application number	US-202117384646-A
Country	US
Kind code	B2
Filing date	Jul 23, 2021
Priority date	Jul 23, 2021
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A processing device includes a zero detection circuit to determine that an operand of a first instruction is zero and instruction conversion logic coupled with the zero detection circuit to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.

First claim

What is claimed is:

1. A processing device, comprising:
a zero value address logic circuit configured to, in response to detecting that a first instance of a load instruction is for storing a zero value, record a source address of the first instance of the load instruction;
a zero detection circuit configured to determine that an operand of a first instruction is zero based on the recorded source address; and
an instruction conversion logic circuit coupled with the zero detection circuit and configured to, in response to the zero detection circuit determining that the operand is zero, convert the first instruction to a register move instruction executable by the processing device.

2. The processing device of claim 1 , further comprising:
a physical register file configured to store a plurality of zero flags each associated with one of a plurality of addresses in the physical register file, wherein the zero detection circuit is further configured to, in response to determining that a load instruction for storing the operand at a destination address in the physical register file is for storing a zero value, assert a zero flag of the plurality of zero flags that is associated with the destination address, wherein the zero detection circuit is configured to determine that the operand is zero by determining that the zero flag is asserted.

3. The processing device of claim 1 , wherein:
the zero detection circuit is further configured to, when execution of the register move instruction causes a zero value to be stored in a destination register of the register move instruction, assert a zero flag associated with the destination register of the register move instruction.

4. The processing device of claim 1 , further comprising:
a load zero value predictor circuit coupled with the instruction conversion logic circuit and configured to:
in response to detecting that the first instance of the load instruction is for storing a zero value, incrementing a confidence counter associated with a program counter of the load instruction; and
in response to detecting that a second instance of the load instruction stores a nonzero value, decreasing the confidence counter.

5. The processing device of claim 4 , wherein:
the load zero value predictor circuit is further configured to, in response to a third instance of the load instruction, assert a zero flag associated with a destination register of the load instruction when the confidence counter associated with the program counter of the load instruction exceeds a confidence threshold, wherein the zero detection circuit is configured to determine that the operand is zero by determining that the zero flag is asserted.

6. The processing device of claim 4 , wherein:
the load zero value predictor circuit is further configured to predict that the operand is zero based on the confidence counter; and
the processing device further comprises a pipeline flush logic circuit configured to perform a pipeline flush in response to determining that an actual value of the operand is nonzero.

7. The processing device of claim 1 , wherein:
the zero value address logic circuit is further configured to:
record the source address of the first instance of the load instruction in an entry of a zero value address table (ZVAT), and
in response to detecting a request to access the source address, invalidate the entry.

8. The processing device of claim 7 , wherein:
the zero value address logic circuit is further configured to detect the request to access the source address by detecting one of an exclusive access request and a modify access request directed to a cache entry for the source address.

9. The processing device of claim 1 , wherein the instruction conversion logic circuit is further configured to:
determine an operand of the register move instruction based on an operation type of the first instruction, wherein the operation type is one of an add, multiply, subtract, and logical AND operation type.

10. The processing device of claim 1 , wherein:
the first instruction is a vectorized instruction; and
the register move instruction is a vectorized register move instruction with a destination register in a vector physical register file.

11. A computing system, comprising:
a memory configured to store an operand for a first instruction; and
a processor coupled with the memory and comprising a zero value address logic circuit configured to, in response to determining that a first instance of a load instruction is for storing a zero value, record a source address of the first instance of the load instruction, wherein the processor is further configured to:
in response to receiving the first instruction, determine that the operand is zero based on the recorded source address,
in response to determining that the operand is zero, convert the first instruction to a register move instruction, and
execute the register move instruction.

12. The computing system of claim 11 , wherein:
the memory comprises a physical register file storing a plurality of zero flags each associated with one of a plurality of addresses in the physical register file, wherein the processor is further configured to, in response to determining that a load instruction for storing the operand at a destination address in the physical register file is for storing a zero value, assert a zero flag of the plurality of zero flags that is associated with the destination address, wherein the processor is configured to determine that the operand is zero by determining that the zero flag is asserted.

13. The computing system of claim 11 , further comprising:
a zero value address table (ZVAT), wherein the zero value address logic circuit configured to:
record the source address of the first load instruction in an entry of the ZVAT, and
in response to determining that a source address of a second load instruction is recorded in an entry of the ZVAT, assert a zero flag associated with a destination address of the second load instruction.

14. A method, comprising:
in response to detecting that a first instance of a load instruction is for storing a zero value, recording a source address of the first instance of the load instruction;
in response to receiving a first instruction in a processor, determining that an operand of the first instruction is zero based on the recorded source address; and
in response to determining that the operand is zero, converting the first instruction to a register move instruction executable by the processor.

15. The method of claim 14 , further comprising:
in response to determining that a load instruction for storing the operand at an address in a physical register file is for storing a zero value, asserting a zero flag associated with the address,
wherein determining that the operand is zero comprises determining that the zero flag associated with the operand is asserted.

16. The method of claim 14 , further comprising:
when execution of the register move instruction causes a zero value to be stored in a destination register, asserting a zero flag associated with the destination register of the register move instruction.

17. The method of claim 14 , further comprising:
in response to detecting that the first instance of the load instruction is for storing a zero value, incrementing a confidence counter associated with a program counter of the load instruction; and
in response to detecting that a second instance of the load instruction stores a nonzero value, decreasing the confidence counter.

18. The method of clai

Assignees

• Advanced Micro Devices Inc

Inventors

• Kalamatianos John
• Dasika Ganesh

Classifications

• G06F9/3832 Primary

  Value prediction for operands; operand history buffers · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F9/30181

  Instruction operation extension or modification · CPC title