Semiconductor device having fins and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-12396205-B2
Application number	US-202418670123-A
Country	US
Kind code	B2
Filing date	May 21, 2024
Priority date	Sep 28, 2017
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A method includes providing a semiconductor structure including a first semiconductor substrate, an insulator layer over the first semiconductor substrate, and a second semiconductor substrate over the insulator layer; patterning the second semiconductor substrate to form a top fin portion over the insulator layer; conformally depositing a protection layer to cover the top fin portion, wherein a first portion of the protection layer is in contact with a top surface of the insulator layer; etching the protection layer to remove a second portion of the protection layer directly over the top fin portion while a third portion of the protection layer still covers a sidewall of the top fin portion; etching the insulator layer by using the third portion of the protection layer as an etch mask; and after etching the insulator layer, removing the third portion of the protection layer.

First claim

What is claimed is:

1. A device, comprising:
a first fin structure comprising:
a first semiconductive bottom portion; and
a first semiconductive top portion over the first semiconductive bottom portion, wherein the first semiconductive bottom portion is wider than the first semiconductive top portion;

a second fin structure comprising:
a second semiconductive bottom portion;
a dielectric middle portion over the second semiconductive bottom portion, wherein a top surface of the first semiconductive bottom portion of the first fin structure is lower than a top surface of the second semiconductive bottom portion of the second fin structure; and
a second semiconductive top portion over the dielectric middle portion; and

an isolation structure extending from the first fin structure to the second fin structure, wherein the isolation structure that extends from the first fin structure to the second fin structure is spaced apart from the dielectric middle portion of the second fin structure.

2. The device of claim 1 , wherein a bottom surface of the first semiconductive top portion of the first fin structure is lower than a bottom surface of the second semiconductive top portion of the second fin structure.

3. The device of claim 2 , wherein a top surface of the first semiconductive top portion of the first fin structure is substantially coplanar with a top surface of the second semiconductive top portion of the second fin structure.

4. The device of claim 1 , wherein the isolation structure is in contact with the first semiconductive top portion of the first fin structure but is spaced apart from the second semiconductive top portion of the second fin structure.

5. The device of claim 1 , wherein the dielectric middle portion of the second fin structure is wider than the second semiconductive top portion of the second fin structure.

6. A device comprising:
a first fin structure over a semiconductor substrate;
a second fin structure over the semiconductor substrate; and
an isolation structure over the semiconductor substrate and between the first and second fin structures, wherein the isolation structure comprises a first sloped bottom surface and a second sloped bottom surface opposing the first sloped bottom surface, the first sloped bottom surface having a bottommost segment level with a bottommost segment of the second sloped bottom surface and a topmost segment higher than a topmost segment of the second sloped bottom surface.

7. The device of claim 6 , wherein the first fin structure comprises an upper portion, a bottom portion, and an insulator layer between the upper portion and the bottom portion.

8. The device of claim 7 , wherein the insulator layer is spaced apart from the isolation structure.

9. The device of claim 7 , wherein a top surface of the insulator layer is in a position higher than a top surface of the isolation structure.

10. The device of claim 7 , wherein the insulator layer is in a position higher than the bottommost segments of the first and second sloped bottom surfaces.

11. The device of claim 7 , further comprising:
a liner layer lining a sidewall of the bottom portion of the first fin structure.

12. The device of claim 7 , further comprising a source/drain epitaxial structure wrapping around the upper portion of the first fin structure.

13. The device of claim 12 , wherein the source/drain epitaxial structure is in direct contact with a top surface of the insulator layer.

14. The device of claim 13 , wherein the source/drain epitaxial structure is further in direct contact with a sidewall of the insulator layer.

15. A device comprising:
a substrate;
a first fin structure over the substrate, wherein the first fin structure comprises:
a bottom semiconductor fin extending from the substrate; and
a top semiconductor fin over the bottom semiconductor fin and formed of a material different from a material of the bottom semiconductor fin, wherein the bottom semiconductor fin comprises a first longitudinal sidewall and a second longitudinal sidewall opposite to the first longitudinal sidewall, the top semiconductor fin comprises a third longitudinal sidewall and a fourth longitudinal sidewall opposing the third longitudinal sidewall, and each of the third and fourth longitudinal sidewalls is offset from both the first and second longitudinal sidewalls;

a second fin structure over the substrate; and
an isolation structure over the substrate and between the first and second fin structures, wherein the isolation structure comprises a first sloped bottom surface and a second sloped bottom surface opposing the first sloped bottom surface, the first sloped bottom surface having a bottommost segment level with a bottommost segment of the second sloped bottom surface and a topmost segment higher than a topmost segment of the second sloped bottom surface.

16. The device of claim 15 , further comprising:
a liner layer lining a sidewall of the bottom semiconductor fin of the first fin structure.

17. The device of claim 15 , wherein the isolation structure surrounds the bottom semiconductor fin of the first fin structure.

18. The device of claim 15 , wherein the second sloped bottom surface of the isolation structure is in a position lower than the first and second longitudinal sidewalls of the bottom semiconductor fin.

19. The device of claim 15 , wherein a width of the bottom semiconductor fin is greater than a width of the top semiconductor fin.

20. The device of claim 15 , wherein the top semiconductor fin over the bottom semiconductor fin is formed of silicon germanium different from silicon of the bottom semiconductor fin.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Kuo Shu-Hao
• Chang Jung-Hao
• Huang Chao-Hsien
• Lin Li-Te
• Ching Kuo-Cheng

Classifications

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title