Semiconductor device and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2017005181-A1
Application number	US-201514820565-A
Country	US
Kind code	A1
Filing date	Aug 7, 2015
Priority date	Jul 1, 2015
Publication date	Jan 5, 2017
Grant date	—

Abstract

A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.

First claim

1 . A semiconductor device, comprising:
a plurality of first fin-shaped structures disposed on a semiconductor substrate, wherein each of the first fin-shaped structures comprises: a base portion disposed on the semiconductor substrate; and a top portion extending from the base portion of the first fin-shaped structure, wherein the top portion of each of the first fin-shaped structure has a first width; a plurality of second fin-shaped structures disposed on the semiconductor substrate, wherein each of the second fin-shaped structures comprises: a base portion disposed on the semiconductor substrate; and a top portion extending from the base portion of the second fin-shaped structure, wherein the top portion of each of the second fin-shaped structure has the first width; and a recessed region disposed on a sidewall of each of the second fin-shaped structures; and a shallow trench isolation disposed between the first fin-shaped structures and the second fin-shaped structures so that portions of each of the top portions protrude from the surface of the shallow trench isolation, wherein the base portions of the second fin-shaped structures are separately disposed on the semiconductor substrate.

2 . The semiconductor device of claim 1 , wherein the base portions of the second fin-shaped structures and the top portions of the second fin-shaped structures have smooth sidewalls.

3 . The semiconductor device of claim 1 , wherein the shallow trench isolation disposed between the second fin-shaped structures is in direct contact with the semiconductor substrate.

4 . The semiconductor device of claim 1 , wherein a top surface of the shallow trench isolation is higher than top surfaces of the base portions of the second fin-shaped structures.

5 . The semiconductor device of claim 1 , further comprising a gate structure covering the top portions protruding from the shallow trench isolation.

6 . The semiconductor device of claim 5 , wherein the gate structure comprises:
a gate dielectric conformally disposed on the top portions; and a gate electrode disposed on the gate dielectric.

7 . A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate having a first region and a second region; forming a patterned mask in the first and second regions of the semiconductor substrate; etching the semiconductor substrate by using the patterned mask as an etch mask so as to form a patterned structure on the surface of the semiconductor substrate; forming a spacer disposed on the sidewall of the patterned structure in the second region; and etching the semiconductor substrate by using the patterned mask and the spacer as an etch mask so as to form a plurality of fin-shaped structures in the first and second regions of the semiconductor substrate.

8 . The method of claim 7 , before the step of forming the spacer, further comprising:
depositing a material layer conformally covering the fin-shaped structures; forming a mask layer covering the material layer in the second region so that the material layer in the first region is exposed from the mask layer; and etching the material layer in the first region by using the mask layer as an etch mask.

9 . The method of claim 7 , wherein the fin-shaped structures comprise:
a plurality of first fin-shaped structures disposed on a semiconductor substrate, wherein each of the first fin-shaped structures comprises: a base portion disposed on the semiconductor substrate; and a top portion extending from the base portion of the first fin-shaped structure, wherein the top portion of each of the first fin-shaped structure has a first width; and a plurality of second fin-shaped structures disposed on the semiconductor substrate, wherein each of the second fin-shaped structures comprises: a base portion disposed on the semiconductor substrate; and a top portion extending from the base portion of the second fin-shaped structure, wherein the top portion of each of the second fin-shaped structure has the first width; and a recessed region disposed on a sidewall of each of the second fin-shaped structures.

10 . The method of claim 7 , wherein the fin-shaped structures are separately disposed on the semiconductor substrate.

11 . The method of claim 7 , wherein the top portions of the fin-shaped structures have equal width.

12 . The method of claim 7 , further comprising:
depositing a dielectric layer to cover the fin-shaped structures; and performing an etching process until each of the fin-shaped structures partially protrudes from a top surface of the dielectric layer.

13 . The method of claim 7 , after the step of forming the fin-shaped structures, further comprising:
removing the spacer; depositing a gate dielectric layer conformally covering the fin-shaped structures; depositing a gate electrode layer covering the gate dielectric layer; and patterning the gate dielectric layer and the gate electrode layer so as to form a gate structure.

14 . The method of claim 7 , further comprising:
forming a mask layer covering the fin-shaped structures in the first region; forming an oxide layer on the sidewalls of the fin-shaped structures in the second region when the fin-shaped structures in the first region are covered by the mask layer, the patterned mask and the spacer; and removing the oxide layer.

Assignees

• United Microelectronics Corp

Inventors

• Liou En-Chiuan
• Tung Yu-Cheng

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10P14/60

  of insulating materials · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10P14/40 Primary

  of conductive or resistive materials · CPC title