Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells

Patent metadata

Field	Value
Publication number	US-12396172-B2
Application number	US-202217713913-A
Country	US
Kind code	B2
Filing date	Apr 5, 2022
Priority date	Apr 5, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A memory array comprising strings of memory cells comprises laterally-spaced memory-blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above conductor material of a conductor tier. Channel-material-string constructions extend through the insulative and conductive tiers to a lowest of the conductive tiers. The channel-material-string constructions individually comprise a charge-blocking-material string, a storage-material string laterally-inward of the charge-blocking-material string, a charge-passage-material string laterally-inward of the storage-material string, and a channel-material string laterally-inward of the charge-passage-material string. A lowest surface of the charge-blocking-material string that is above a lowest surface of the lowest conductive tier is below a lowest surface of a lowest of the insulative tiers that is immediately-above the lowest conductive tier. Conductive material in the lowest conductive tier directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Structure independent of method is disclosed.

First claim

The invention claimed is:

1. A method used in forming a memory array comprising strings of memory cells, comprising:
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above conductor material of a conductor tier;
forming channel-material structures that extend through the first and second tiers to a lowest of the first tiers, the channel-material-structures individually comprising a charge-blocking-material, a storage-material radially-inward of the charge-blocking-material, a charge-passage-material radially-inward of the storage-material, and a channel material radially-inward of the charge-passage-material;
etching the charge-blocking-material upwardly from and through the lowest first tier selectively relative to the storage-material;
after the etching of the charge-blocking-material, etching the storage-material and the charge-passage-material in the lowest first tier to expose the channel material in the lowest first tier; and
forming conductive material in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material structures and the conductor material of the conductor tier.

2. The method of claim 1 wherein the channel-material structures extend into the conductor tier.

3. The method of claim 1 wherein the etching of the charge-blocking-material through the lowest first tier etches the charge-blocking-material downwardly from the lowest first tier selectively relative to the storage-material.

4. The method of claim 1 wherein the etching of the storage-material and the charge-passage-material in the lowest first tier etches the storage-material and the charge-passage-material upwardly from and through the lowest first tier selectively relative to the channel material.

5. The method of claim 1 wherein the upwardly etching of the charge-blocking-material leaves a lowest surface of the charge-blocking-material that is above a lowest surface of the lowest first tier to be below a lowest surface of a lowest of the second tiers that is immediately-above the lowest first tier.

6. The method of claim 5 wherein the etching of the storage-material and the charge-passage-material string in the lowest first tier etches the storage-material and the charge-passage-material upwardly from and through the lowest first tier selectively relative to the channel-material to leave respective lowest surfaces of the storage-material and the charge-passage-material that are above the lowest surface of the lowest first tier to be below the lowest surface of the lowest second tier that is immediately-above the lowest first tier.

7. The method of claim 6 wherein the lowest surfaces above the lowest surface of the lowest first tier of the charge-blocking-material, the storage-material, and the charge-passage-material are planar and coplanar.

8. The method of claim 1 wherein the conductive material in the lowest first tier is directly against a laterally-outer sidewall of the channel material.

9. A method used in forming a memory array comprising strings of memory cells, comprising:
forming laterally-spaced memory-block regions individually comprising a vertical stack comprising alternating first tiers and second tiers directly above conductor material of a conductor tier;
forming channel-material structures that extend through the first and second tiers to a lowest of the first tiers, the channel-material structures individually comprising a charge-blocking-material, a storage-material radially-inward of the charge-blocking-material, a charge-passage-material radially-inward of the storage-material, and a channel material radially-inward of the charge-passage-material;
etching the charge-blocking-material, the storage-material, and the charge-passage-material in the lowest first tier to expose the channel material in the lowest first tier; the etching leaving a lowest surface of the charge-blocking-material that is above a lowest surface of the lowest first tier to be below a lowest surface of a lowest of the second tiers that is immediately-above the lowest first tier; and
forming conductive material in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material structures and the conductor material of the conductor tier.

10. The method of claim 9 wherein the etching of the storage-material and the charge-passage-material in the lowest first tier etches the storage-material and the charge-passage-material upwardly from and through the lowest first tier selectively relative to the channel material to leave respective lowest surfaces of the storage-material and the charge-passage-material that are above the lowest surface of the lowest first tier to be below the lowest surface of the lowest second tier that is immediately-above the lowest first tier.

11. The method of claim 9 wherein the conductive material in the lowest first tier is directly against a laterally-outer sidewall of the channel material.

12. The method of claim 10 wherein the lowest surfaces above the lowest surface of the lowest first tier of the charge-blocking-material, the storage-material, and the charge-passage-material are planar and coplanar.

13. The method of claim 9 wherein the conductive material in the lowest first tier is directly against a laterally-outer sidewall of the channel material.

Assignees

• Micron Technology Inc

Inventors

• Howder Collin
• Ehorn Jeffrey
• Hopkins John D

Classifications

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title