Method of fabricating three-dimensional NAND memory

Patent metadata

Field	Value
Publication number	US-12396171-B2
Application number	US-202217709668-A
Country	US
Kind code	B2
Filing date	Mar 31, 2022
Priority date	May 14, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

The present disclosure provides a method for forming a three-dimensional (3D) memory device. The method includes forming a dielectric stack on a substrate, and forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack. The method also includes forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening. The method further includes removing a portion of the first layer located at the bottom of the first opening from a second side of the dielectric stack to expose a portion of the second layer. The method further includes forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack on a substrate;
forming a first opening penetrating through the dielectric stack and extending into the substrate from a first side of the dielectric stack that is farther away from the substrate;
forming a first layer and a second layer inside the first opening from the first side of the dielectric stack, wherein the first layer covers a sidewall and a bottom of the first opening;
removing the substrate from a second side of the dielectric stack to expose a portion of the first layer located at the bottom of the first opening, wherein the second side of the dielectric stack is opposite to the first side of the dielectric stack;
removing the portion of the first layer located at the bottom of the first opening from the second side of the dielectric stack to expose a portion of the second layer; and
after removing a first semiconductor layer, forming a second semiconductor layer from the second side of the dielectric stack to contact the exposed portion of the second layer.

2. The method of claim 1 , wherein the removing the substrate includes:
removing a handle wafer from an insulator layer;
removing the insulator layer from the first semiconductor layer; and
removing the first semiconductor layer from the first layer.

3. The method of claim 1 , further including:
prior to forming the dielectric stack, disposing a first etch-stop layer and a second etch-stop layer on the substrate; and
disposing the dielectric stack on the second etch-stop layer.

4. The method of claim 3 , further including removing the substrate from the first etch-stop layer and the first layer from the second side of the dielectric stack to expose the portion of the first layer located at the bottom of the first opening.

5. The method of claim 4 , further including removing the exposed portion of the first layer and the first etch-stop layer from the second etch-stop layer from the second side of the dielectric stack to expose the portion of the second layer.

6. The method of claim 5 , further including disposing the second semiconductor layer on the second etch-stop layer and the exposed portion of the second layer from the second side of the dielectric stack.

7. The method of claim 1 , wherein the forming the second semiconductor layer to contact the exposed portion of the second layer includes disposing an array common source to contact the exposed portion of the second layer.

8. The method of claim 1 , wherein the forming the first opening, the forming the first layer and the second layer, the removing the portion of the first layer, and the forming the second semiconductor layer include:
forming a channel hole penetrating through the dielectric stack and extending into the substrate from the first side of the dielectric stack;
forming a memory film and a channel layer on a sidewall and a bottom of the channel hole from the first side of the dielectric stack;
removing a portion of the memory film located at the bottom of the channel hole to expose a portion of the channel layer from the second side of the dielectric stack; and
forming the second semiconductor layer to contact the exposed portion of the channel layer from the second side of the dielectric stack.

9. The method of claim 1 , wherein the forming the first opening, the forming the first layer and the second layer, the removing the portion of the first layer, and the forming the second semiconductor layer include:
forming a gate line slit (GLS) opening penetrating through the dielectric stack and extending into the substrate from the first side of the dielectric stack;
after forming a first GLS isolation layer, forming a second GLS isolation layer and a GLS filler inside the GLS opening from the first side of the dielectric stack;
removing a portion of the second GLS isolation layer to expose a portion of the GLS filler from the second side of the dielectric stack; and
forming the second semiconductor layer to contact the exposed portion of the second GLS isolation layer from the second side of the dielectric stack.

10. The method of claim 9 , further including:
prior to forming the second GLS isolation layer, disposing a first sub-layer insulator inside the GLS opening at a first temperature;
disposing a second sub-layer insulator on the first sub-layer insulator inside the GLS opening at a second temperature higher than the first temperature; and
removing portions of the first sub-layer insulator and the second sub-layer insulator located on the bottom of the GLS opening to expose a portion of the substrate.

11. The method of claim 9 , wherein the forming the dielectric stack includes disposing, alternatingly, a first dielectric layer and a second dielectric layer on the substrate.

12. The method of claim 11 , further including replacing the second dielectric layer with a conductive layer through the GLS opening to form a film stack of alternating conductive and dielectric layers.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Liu Yaqin
• Zhang Kun
• Wu Linchun
• Zhou Wenxi

Classifications

• H10P95/11

  Separation of active layers from substrates · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/41

  of a memory region comprising a cell select transistor, e.g. NAND · CPC title