Semiconductor device and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12396159-B2
Application number	US-202217969966-A
Country	US
Kind code	B2
Filing date	Oct 20, 2022
Priority date	Oct 28, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Provided is a semiconductor device including a substrate including a cell array area and a peripheral circuit area and including a plurality of first active areas defined in the cell array area and at least one second active area defined in the peripheral circuit area; a plurality of bit lines arranged in the cell array area of the substrate and extending in a first direction; a plurality of cell pad structures arranged between the bit lines and each including a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of the first active area; and a peripheral circuit gate electrode disposed on the peripheral circuit area of the substrate and including a second conductive layer, a second intermediate layer, and a second metal layer sequentially arranged on the at least one second active area.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising a cell array area, a peripheral circuit area, a plurality of first active areas defined in the cell array area, and at least one second active area defined in the peripheral circuit area;
a plurality of bit lines in the cell array area of the substrate and extending in a first direction;
a plurality of cell pad structures between the plurality of bit lines and each comprising a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of a respective one of the plurality of first active areas; and
a peripheral circuit gate electrode on the peripheral circuit area of the substrate and comprising a second conductive layer, a second intermediate layer, and a second metal layer that are sequentially arranged on the at least one second active area.

2. The semiconductor device of claim 1 ,
wherein the first conductive layer comprises a same first material as the material included in the second conductive layer,
the first intermediate layer comprises a same second material as the material included in the second intermediate layer, and
the first metal layer comprises a same third material as the material included in the second metal layer.

3. The semiconductor device of claim 1 , wherein the first conductive layer covers a top surface and side surfaces of each of the first active areas.

4. The semiconductor device of claim 1 , further comprising:
a bit line contact between the bit lines and the first active areas;
a bit line contact spacer between the bit line contact and a respective one of the plurality of cell pad structures; and
bit line spacers on sidewalls of the plurality of bit lines.

5. The semiconductor device of claim 4 ,
wherein the bit line contact comprises a metal material, and
the bit line contact contacts top surfaces of the first active areas.

6. The semiconductor device of claim 4 ,
wherein sidewalls of the first conductive layer of the plurality of cell pad structures contact the bit line contact spacer, and
sidewalls of the first metal layer of the plurality of cell pad structures contact the bit line spacers.

7. The semiconductor device of claim 1 ,
wherein the substrate further comprises a boundary area between the cell array area and the peripheral circuit area, and
the semiconductor device further comprises: a boundary structure in a boundary trench extending into the boundary area, the boundary structure comprising an insulation material; and
a buffer layer on the boundary structure.

8. The semiconductor device of claim 7 , wherein at least one of the cell pad structures extends onto the boundary structure.

9. The semiconductor device of claim 8 , wherein the at least one of the cell pad structures comprises a first portion and a second portion, the first portion is on the first active areas, and the second portion is on the buffer layer.

10. The semiconductor device of claim 1 ,
wherein the first metal layer has a first height in a vertical direction,
the second metal layer has a second height in the vertical direction, and
the second height is same as the first height.

11. The semiconductor device of claim 10 ,
wherein the bit lines have a third height in the vertical direction, and
the third height is different from the first height and is different from the second height.

12. The semiconductor device of claim 1 ,
wherein the peripheral circuit gate electrode further comprises a third metal layer disposed on the second metal layer, and
the third metal layer comprises a same material as the material included in the bit lines.

13. The semiconductor device of claim 12 ,
wherein the bit lines have a third height in a vertical direction, the third metal layer has a fourth height in the vertical direction, and
the fourth height is same as the third height.

14. A semiconductor device comprising:
a substrate comprising a cell array area, a boundary area, a peripheral circuit area, a plurality of first active areas defined in the cell array area, and at least one second active area defined in the peripheral circuit area;
a plurality of bit lines in the cell array area of the substrate and extending in a first direction;
a plurality of cell pad structures arranged between two adjacent bit lines from among the plurality of bit lines and each comprising a first conductive layer and a first metal layer that are sequentially arranged on a top surface of a respective one of the plurality of the first active area; and
a peripheral circuit gate electrode on the peripheral circuit area of the substrate and comprising a second conductive layer and a second metal layer that are sequentially arranged on the at least one second active area,
wherein a first height of the cell pad structures is same as a second height of the peripheral circuit gate electrode.

15. The semiconductor device of claim 14 , further comprising:
a bit line contact disposed between the bit lines and the first active areas;
a bit line contact spacer disposed between the bit line contact and a respective one of the plurality of cell pad structures; and
bit line spacers arranged on sidewalls of the bit lines.

16. The semiconductor device of claim 15 ,
wherein sidewalls of the first conductive layer of the plurality of cell pad structures contact the bit line contact spacer, and
sidewalls of the first metal layer of the cell pad structure contact the bit line spacers.

17. The semiconductor device of claim 14 ,
wherein the first conductive layer comprises a same first material as the material included in the second conductive layer, and
the first metal layer comprises a same second material as the material included in the second metal layer.

18. The semiconductor device of claim 14 , further comprising:
a boundary structure in a boundary trench extending into the boundary area, the boundary structure comprising an insulation material; and
a buffer layer on the boundary structure,
wherein at least one of the cell pad structures extends onto the boundary structure.

19. The semiconductor device of claim 14 ,
wherein the first metal layer has a first height in a vertical direction,
the second metal layer has a second height in the vertical direction, and
the second height is same as the first height.

20. A semiconductor device comprising:
a substrate comprising a cell array area, a boundary area, a peripheral circuit area, a plurality of first active areas defined in the cell array area, and at least one second active area defined in the peripheral circuit area;
a plurality of bit lines in the cell array area of the substrate and extending in a first direction;
a bit line contact disposed between the bit lines and the first active areas and electrically connecting the bit lines to the first active areas;
a bit line contact spacer surrounding sidewalls of the bit line contact;
a plurality of cell pad structures between two adjacent bit lines from among the plurality of bit lines and each comprising a first conductive layer, a first intermediate layer, and a first metal layer that are sequentially arranged on a top surface of a respective one of the plurality of first active areas;
a plurality of landing pads respectively arranged on the cell pad structures; and
a peripheral circuit gate electrode on the peripheral circuit area of the substrate and comprising a second conductive layer, a second intermediate layer, and a secon

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Junhyeok
• Park Sohyun
• Kim Hyosub

Classifications

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/482

  Bit lines · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/09

  with simultaneous manufacture of the peripheral circuit region and memory cells · CPC title