Integrated circuit interconnect structures with graphene cap

Patent metadata

Field	Value
Publication number	US-12394716-B2
Application number	US-202117358962-A
Country	US
Kind code	B2
Filing date	Jun 25, 2021
Priority date	Jun 25, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a plurality of transistors; and
an interconnect structure coupled to at least one of the transistors, wherein the interconnect structure comprises:
a first metal; and
graphene over, and in direct contact with, a top surface of the first metal, wherein the graphene comprises a plurality of grains spaced apart from adjacent grains,
wherein an amount of a second metal, nitrogen or silicon within the first metal is higher proximal to an interface of the graphene than distal from the interface, and higher within a first region of the first metal below spaces between the grains than within a second region of the first metal immediately below individual ones of the grains.

2. The IC structure of claim 1 , wherein the amount of the second metal is higher proximal to the interface, and wherein the second metal is Mn, Zn, Mg, Co, or Al.

3. The IC structure of claim 2 , wherein the second metal is Mn or Zn.

4. The IC structure of claim 3 , wherein the second metal is Mn.

5. The IC structure of claim 2 , wherein the first metal is Cu, Ru, Co, Mo, or W.

6. The IC structure of claim 5 , wherein the first metal is Cu.

7. The IC structure of claim 1 , wherein the second metal, nitrogen or silicon is substantially absent from the first metal at distances greater than 5 nm of the interface.

8. The IC structure of claim 1 , wherein the interconnect structure further comprises a third metal in contact with a bottom of the first metal, opposite the graphene, and between the first metal and an underlying dielectric material.

9. The IC structure of claim 8 , wherein the third metal is at least one of Co, Ta, or Ti.

10. The IC structure of claim 8 , wherein the third metal is in contact with a sidewall of the first metal, and between the first metal and an adjacent dielectric material.

11. The IC structure of claim 1 , wherein
a dielectric material is over the graphene, and within the spaces between the grains.

12. A computer platform comprising:
a power supply; and
an integrated circuit (IC) coupled to the power supply, wherein the IC comprises the IC structure of claim 1 .

13. The platform of claim 12 , wherein:
the first metal is Cu;
and
the second metal is Mn or Zn.

14. The platform of claim 13 , wherein
the interconnect structure further comprises a third metal in contact with a bottom of the first metal, opposite the graphene, and between a sidewall of the first metal and an adjacent dielectric material;
the third metal is at least one of Co, Ta, or Ti.

15. The platform of claim 13 , wherein the second metal is substantially absent from the first metal at distances greater than 5 nm of the interface.

16. A method of forming an integrated circuit (IC) interconnect structure, comprising:
depositing a first metal over a dielectric material;
forming graphene directly on a top surface of the first metal; and
doping first regions of the first metal that are below spaces between grains of the graphene with a concentration of a second metal, nitrogen or silicon that is higher than within second regions of the first metal that are immediately below individual ones of the grains.

17. The method of claim 16 , wherein:
depositing the first metal comprises depositing a seed layer comprising Cu, and electroplating Cu or a Cu alloy upon the seed layer.

18. The method of claim 17 , wherein the second metal comprises Mn, Zn, Mg, or Co.

19. The method of claim 16 , wherein doping the first regions of the first metal with the second metal, nitrogen, or silicon comprises introducing Al, N, or Si into at least the top surface of the first metal.

Assignees

• Intel Corp

Inventors

• Naylor Carl
• Chawla Jasmeet
• Metz Matthew
• King Sean
• Chebiam Ramanan
• Kobrinsky Mauro
• Clendenning Scott
• Lee Sudarat
• Jezewski Christopher
• Chugh Sunny
• Bielefeld Jeffery

Classifications

• H10P32/30

  Diffusion for doping of conductive or resistive layers · CPC title

• H10W20/038

  covering conductive structures (H10W20/037 takes precedence) · CPC title

• H10W20/0372

  comprising multiple barrier, adhesion or liner layers · CPC title

• H10W20/4462

  Carbon or carbon-containing materials, e.g. graphene · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title