Interconnect structures with variable dopant levels

Patent metadata

Field	Value
Publication number	US-9768065-B1
Application number	US-201615203084-A
Country	US
Kind code	B1
Filing date	Jul 6, 2016
Priority date	Jul 6, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

Interconnect structures and related methods of manufacture improve device reliability and performance by selectively incorporating dopants into conductive lines. Multiple seed layer deposition steps or variable trench bottom areas are used to locally control the dopant concentration within the interconnect structures at the same wiring level, which provides a robust integration approach for metallizing interconnects in future-generation technology nodes.

First claim

What is claimed as new is:

1. An integrated circuit comprising:
a first interconnect and a second interconnect at the same wiring level over a semiconductor substrate; and
a dielectric capping layer over a top surface of the first and second interconnect structures, wherein the first interconnect comprises a first bulk metal layer having a first dopant concentration and the second interconnect comprises a second bulk metal layer having a second dopant concentration different from the first dopant concentration.

2. The integrated circuit according to claim 1 , further comprising a dielectric layer over the semiconductor substrate, wherein the first interconnect is disposed within a first trench in the dielectric layer and the second interconnect is disposed within a second trench in the dielectric layer.

3. The integrated circuit according to claim 2 , wherein the first interconnect is disposed within a structure selected from the group consisting of a dummy via and a microtrench located in a bottom surface of the trench.

4. The integrated circuit according to claim 3 , wherein the structure comprises a plurality of parallel microtrenches.

5. The integrated circuit according to claim 3 , wherein the first dopant concentration is greater than the second dopant concentration.

6. The integrated circuit according to claim 1 , wherein the first interconnect has a first end portion separated from a second end portion by an intermediate portion and a dopant concentration within the first end portion is different than a dopant concentration within the second end portion.

7. The integrated circuit according to claim 1 , wherein the first interconnect has a first end portion separated from a second end portion by an intermediate portion and a dopant concentration within each of the first and second end portions is different than a dopant concentration within the intermediate portion.

8. The integrated circuit according to claim 1 , comprising a first metal alloy layer between the dielectric capping layer and the bulk metal layer of the first interconnect, and a second metal alloy layer between the dielectric capping layer and the bulk metal layer of the second interconnect, wherein the first metal alloy layer is thicker than the second metal alloy layer.

9. The integrated circuit according to claim 8 , wherein the first and second metal alloy layers comprise a reaction product of the dielectric capping layer and a dopant.

10. The integrated circuit according to claim 9 , wherein the first and second metal alloy layers each comprise copper and manganese.

11. The integrated circuit according to claim 1 , wherein the first interconnect is a power interconnect and comprises a first alloy of copper and manganese, and the second interconnect is a signal interconnect and comprises a second alloy of copper and manganese, wherein the first alloy has a concentration of manganese greater than the second alloy.

12. A method of forming an integrated circuit, comprising:
forming a first interconnect and a second interconnect within respective first and second trenches at a same wiring level;
forming a first seed layer within the first trench and a second seed layer within the second trench, the first seed layer having a different dopant concentration than the second seed layer;
forming a structure selected from the group consisting of a dummy via and a microtrench within a bottom surface of at least one of the first trench and the second trench prior to forming the first and second seed layers;
forming a first dopant concentration within the first interconnect; and
forming a second dopant concentration within the second interconnect different from the first dopant concentration.

13. The method according to claim 12 , wherein forming the structure comprises forming a plurality of parallel microtrenches.

Assignees

• Globalfoundries Inc

Inventors

• Wang Ping-Chuan
• Kaltalioglu Erdem
• Filippi Ronald G
• Christiansen Cathryn J

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/4424

  Copper alloys · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title