Superconducting device including set of circuits having different operational temperature requirements with multiple thermal sinks and multiple ground planes

Patent metadata

Field	Value
Publication number	US-12394688-B2
Application number	US-202418630530-A
Country	US
Kind code	B2
Filing date	Apr 9, 2024
Priority date	Dec 20, 2018
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

First claim

What is claimed is:

1. A circuit comprising:
a first dielectric layer comprising a first electrically conducting ground plane and a first set of circuits that have a first operational temperature requirement, the first dielectric layer further comprising a second electrically conducting ground plane and a second set of circuits that have a different operational temperature requirement than the first electrically conducting ground plane and the first set of circuits;
a second dielectric layer comprising a third electrically conducting ground plane and a third set of circuits that have a third operational temperature requirement, the second dielectric layer further comprising a fourth electrically conducting ground plane and a fourth set of circuits that have a different operational temperature requirement than the third electrically conducting ground plane and the third set of circuits;
a plurality of thermal sink layers; and
a plurality of conductive vias,
wherein at least one conductive via of the plurality of conductive vias couples one of the first, second, third, and fourth electrically conducting ground planes to one of the plurality of thermal sink layers.

2. The circuit of claim 1 , wherein each thermal sink layer of the plurality of thermal sink layers is cooled at a different temperature to maintain the first, second, third, and fourth set of circuits at different operational temperatures.

3. The circuit of claim 1 , wherein the first electrically conducting ground plane and the first set of circuits are adjacent to and physically separated from the second electrically conducting ground plane and the second set of circuits.

4. The circuit of claim 3 , wherein the third electrically conducting ground plane and the third set of circuits are adjacent to and physically separated from the fourth electrically conducting ground plane and the fourth set of circuits.

5. The circuit of claim 1 , wherein the plurality of thermal sink layers comprises:
a first thermal sink layer;
a second thermal sink layer;
a third thermal sink layer; and
a fourth thermal sink layer.

6. The circuit of claim 5 , wherein the first thermal sink layer and the second thermal sink layer are separated by a first separation region, and the third thermal sink layer and the fourth thermal sink layer are separated by a second separation region.

7. The circuit of claim 6 , wherein the plurality of conductive vias comprises:
a first conductive via;
a second conductive via;
a third conductive via; and
a fourth conductive via.

8. The circuit of claim 7 , wherein the first conductive via couples the first electrically ground plane to the first thermal sink layer, the second conductive via couples the second electrically ground plane to the second thermal sink layer, the third conductive via couples the third electrically ground plane to the third thermal sink layer, and the fourth conductive via couples the fourth electrically ground plane to the fourth thermal sink layer.

9. The circuit of claim 1 , wherein the plurality of thermal sink layers and the plurality of conductive vias are formed of copper.

10. The circuit of claim 1 , wherein the first, second, third, and fourth set of circuits correspond to first, second, third, and fourth set of superconducting circuits.

11. The circuit of claim 1 , wherein the circuit is a Monolithic Microwave Integrated circuit.

Assignees

• Northrop Grumman Systems Corp

Inventors

• Hathaway Aaron Ashley
• Boyd Gregory R
• Przybysz John X

Classifications

• H10W44/251

  for monolithic microwave integrated circuits [MMIC] · CPC title

• H10W44/203

  Electrical connections · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/4484

  Superconducting materials · CPC title

• H10W20/427

  Power or ground buses · CPC title