Semiconductor memory device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12394482-B2
Application number	US-202217687085-A
Country	US
Kind code	B2
Filing date	Mar 4, 2022
Priority date	Sep 17, 2021
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

According to one embodiment, a semiconductor memory device includes: a first chip including first conductive layers arranged at intervals in a first direction, a first semiconductor layer extending through an inside of the first conductive layers in the first direction, a first insulating film between the first semiconductor layer and the first conductive layers, a second semiconductor layer provided above the first conductive layers and in contact with the first semiconductor layer, and a first electrode provided in contact with an upper side of the second semiconductor layer; and a second chip including a second electrode in contact with the first electrode, and a second conductive layer in contact with the second electrode.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first memory cell chip including:
a plurality of first conductive layers arranged at intervals in a first direction,
first insulators alternately arranged with respect to the plurality of first conductive layers in the first direction,
a first semiconductor layer extending in the first direction through the plurality of first conductive layers,
a first insulating film disposed between the first semiconductor layer and the plurality of first conductive layers,
a first source line extending in a second direction perpendicular to the first direction to be in contact with a plural number of the first semiconductor layers and a plural number of the first insulating films, and
a first electrode disposed in contact with an upper side of the first source line; and

a second memory cell chip including:
a second electrode in contact with the first electrode, and
a second source line extending in the second direction and in contact with the second electrode.

2. The semiconductor memory device according to claim 1 , wherein the second conductive layer source line contains copper (Cu).

3. The semiconductor memory device according to claim 1 , wherein the second memory cell chip further includes:
a plurality of third conductive layers arranged at intervals in the first direction;
a third semiconductor layer extending in the first direction through the third conductive layers;
a second insulating film disposed between the third semiconductor layer and the third conductive layers;
a third source line extending in the second direction to be in contact with a plural number of the third semiconductor layers and a plural number of the second insulating films; and
a fourth source line extending in the second direction and connected to at least the third source line.

4. The semiconductor memory device according to claim 3 , wherein at least one of the second source line or the fourth source line contains aluminum (Al).

5. The semiconductor memory device according to claim 1 , wherein
the second source line and the first source line are electrically connected via the first electrode and the second electrode.

6. The semiconductor memory device according to claim 1 , further comprising:
a third memory cell chip including a transistor and a third electrode,
wherein the first memory cell chip further includes a fourth electrode in contact with the third electrode.

7. The semiconductor memory device according to claim 1 , wherein the second memory cell chip further includes a third electrode,
the semiconductor memory device further includes a third memory cell chip including a fourth electrode, the fourth electrode in contact with the third electrode,
the third memory cell chip further includes:
a plurality of third conductive layers arranged at intervals in the first direction;
a third semiconductor layer extending in the first direction through the third conductive layers;
a second insulating film between the third semiconductor layer and the third conductive layers; and
a fifth source line extending in the second direction to be in contact with a plural number of the third semiconductor layers and the third electrode, and

the third memory cell chip further includes a sixth source line in contact with the fourth electrode.

8. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device is a NAND-type flash memory.

9. A semiconductor memory device comprising:
a plurality of memory cell chips arranged in a first direction,
wherein a lowermost one of the memory cell chips includes:
a plurality of first conductive layers arranged at intervals in the first direction;
a plurality of first insulators alternately arranged with respect to the plurality of first conductive layers in the first direction;
a first semiconductor layer extending in the first direction to extend through the first conductive layers;
a first insulating film disposed between the first semiconductor layer and the first conductive layers;
a first source line extending in a second direction perpendicular to the first direction to be in contact with a plural number of the first semiconductor layers and a plural number of the first insulating films; and
a first electrode disposed in contact with an upper side of the first source line, the first electrode connected to the lowermost cell memory chip, and

an uppermost one of the memory cell chips includes:
a second electrode connected the uppermost memory cell chip;
a second source line in contact with the second electrode;
a plurality of third conductive layers arranged at intervals in the first direction and disposed above the second source line;
a second semiconductor layer extending in the first direction to extend through the third conductive layers;
a second insulating film disposed between the third second semiconductor layer and the third conductive layers;
a third source line extending in the second direction to be in contact with the second semiconductor layer and disposed above the third conductive layers; and
a fourth source line extending in the second direction and connected to the third source line.

10. The semiconductor memory device according to claim 1 , wherein the first source line and the second source line include silicon.

11. The semiconductor memory device according to claim 1 , wherein the first insulating film includes silicon oxide.

12. The semiconductor memory device according to claim 3 , wherein the second insulating film includes silicon oxide.

13. The semiconductor memory device according to claim 1 , wherein the first conductive layers include at least one of copper or aluminum.

14. The semiconductor memory device according to claim 1 , wherein the first memory cell chip and the second memory cell chip are bonded to each other.

15. The semiconductor memory device according to claim 7 , wherein the third memory cell chip and the second memory cell chip are bonded to each other.

16. The semiconductor memory device according to claim 9 , wherein adjacent ones of the plurality of memory cell chips are bonded to each other.

17. The semiconductor memory device according to claim 1 , wherein the first memory cell chip further includes:
a contact plug extending in the first direction, and
the second source line and the contact plug are electrically connected via the first electrode and the second electrode in an area separated from the first conductive layers.

18. A semiconductor memory device comprising:
a first memory cell chip including:
a transistor and a plurality of first electrodes disposed over the transistor;

a second memory cell chip including:
a plurality of a second electrodes in contact with the first electrodes,
a plurality of first conductive layers arranged at intervals in a first direction,
a first semiconductor pillar extending in the first direction to extend through the first conductive layers,
a first insulating film disposed between the first semiconductor pillar and the first conductive layers,
a first source line extending in a second direction perpendicular to the first direction, disposed above the first conductive layers, and in contact with a plural number of the first semiconductor pillars,
a third electrode disposed in contact with an upper side of the first source line, and
a contact plug extending through in the first direction and connecting the second electrode and the third electrode in an area separated from the first conductive lay

Assignees

• Kioxia Corp

Inventors

• Kume Ippei

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/20

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title