Semiconductor chip capable of calibrating bias voltage supplied to write clock buffer regardless of process variation and temperature variation, and devices including the same

Patent metadata

Field	Value
Publication number	US-12394470-B2
Application number	US-202318221598-A
Country	US
Kind code	B2
Filing date	Jul 13, 2023
Priority date	Oct 6, 2022
Publication date	Aug 19, 2025
Grant date	Aug 19, 2025

Abstract

A semiconductor chip includes a write clock buffer, a voltage regulator, a process calibration circuit and a temperature calibration circuit. The voltage regulator generates plural regulated voltages. The process calibration circuit output one of the regulated voltages as a bias voltage of the write clock buffer, depending on a process variation of the semiconductor chip. The temperature calibration circuit track a temperature variation of the semiconductor chip in real time, performs analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and outputs the analog-calibrated bias voltage to the write clock buffer.

First claim

What is claimed is:

1. A semiconductor chip comprising:
a write clock buffer;
a voltage regulator configured to generate a plurality of regulated voltages;
a process calibration circuit configured to output one of the plurality of regulated voltages as a bias voltage of the write clock buffer, depending on a process variation of the semiconductor chip; and
a temperature calibration circuit configured to track a temperature variation of the semiconductor chip in real time, perform analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and output the analog-calibrated bias voltage to the write clock buffer.

2. The semiconductor chip of claim 1 , wherein the process calibration circuit includes a replica write clock buffer including a bias transistor, and the process calibration circuit is configured to output the one of the plurality of regulated voltages using digital signals such that a threshold voltage of the bias transistor is calibrated, the threshold voltage changing depending on the process variation, and
wherein the temperature calibration circuit is configured to output the analog-calibrated bias voltage to the write clock buffer, the analog-calibrated bias voltage being inversely proportional to the temperature variation.

3. The semiconductor chip of claim 2 , further comprising:
a control logic circuit,
wherein, while the temperature calibration circuit is enabled based on a first control signal, the control logic circuit is configured to enable the process calibration circuit based on the first control signal and disable the process calibration circuit after a given time passes following receipt of the first control signal.

4. The semiconductor chip of claim 2 , wherein a structure of the write clock buffer is identical to a structure of the replica write clock buffer, and
wherein each of the write clock buffer and the replica write clock buffer is a current mode logic buffer.

5. The semiconductor chip of claim 2 , wherein the temperature calibration circuit is connected between a current output node of the voltage regulator and a ground, and includes:
at least one diode-connected transistor;
a switch circuit configured to connect the current output node and the at least one diode-connected transistor based on a first control signal; and
a transistor configured to transfer a current of the at least one diode-connected transistor to the ground based on the first control signal.

6. The semiconductor chip of claim 5 , wherein a threshold voltage of the at least one diode-connected transistor is lower than the threshold voltage of the bias transistor.

7. The semiconductor chip of claim 5 , wherein the at least one diode-connected transistor has a negative temperature coefficient characteristic.

8. The semiconductor chip of claim 2 , wherein the process calibration circuit includes:
a multiplexer configured to output the one of the plurality of regulated voltages to a gate of the bias transistor and to the write clock buffer based on to the digital signals;
a control logic circuit configured to generate a second control signal for enabling the replica write clock buffer based on a first control signal;
a comparator configured to compare a reference voltage and an output signal of the replica write clock buffer and output a comparison signal; and
a counter configured to generate the digital signals corresponding to a count value based on an oscillation signal and the comparison signal.

9. The semiconductor chip of claim 8 , wherein, while the temperature calibration circuit is enabled based on the first control signal, the control logic circuit is configured to generate the second control signal, and
wherein the second control signal that is generated is identical to the first control signal for enabling the replica write clock buffer and is different from the first control signal for disabling the replica write clock buffer.

10. A memory device comprising:
a bias circuit configured to generate a bias voltage; and
a write clock buffer configured to buffer complementary write clock signals based on the bias voltage and generate buffered complementary write clock signals,
wherein the bias circuit comprises:
a voltage regulator configured to generate a plurality of regulated voltages;
a process calibration circuit configured to output one of the plurality of regulated voltages as the bias voltage to the write clock buffer, depending on a process variation of the memory device; and
a temperature calibration circuit configured to track a temperature variation of the memory device in real time, perform analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and output the analog-calibrated bias voltage to the write clock buffer.

11. The memory device of claim 10 , wherein the memory device is an LPDDR DRAM.

12. The memory device of claim 10 , wherein the process calibration circuit includes a replica write clock buffer including a bias transistor, and the process calibration circuit is configured to output the one of the plurality of regulated voltages as the bias voltage to the write clock buffer using digital signals such that a threshold voltage of the bias transistor is calibrated, the threshold voltage changing depending on the process variation, and
wherein the temperature calibration circuit is configured to output the analog-calibrated bias voltage in real time to the write clock buffer, the analog-calibrated bias voltage being inversely proportional to the temperature variation.

13. The memory device of claim 12 , further comprising:
a control logic circuit,
wherein, while the temperature calibration circuit is enabled based on a first control signal, the control logic circuit is configured to enable the process calibration circuit based on the first control signal and disable the process calibration circuit after a given time passes following receipt of the first control signal.

14. The memory device of claim 12 , wherein the temperature calibration circuit includes a plurality of diode-connected transistors, and
wherein a threshold voltage of each of the plurality of diode-connected transistors is lower than the threshold voltage of the bias transistor.

15. A memory system comprising:
a memory device; and
a system on chip configured to control an operation of the memory device,
wherein the memory device comprises:
a bias circuit configured to generate a bias voltage; and
a write clock buffer configured to buffer complementary write clock signals by using the bias voltage and generate buffered complementary write clock signals, and

wherein the bias circuit comprises:
a voltage regulator configured to generate a plurality of regulated voltages;
a process calibration circuit configured to output one of the plurality of regulated voltages as the bias voltage to the write clock buffer, depending on a process variation of the memory device; and
a temperature calibration circuit configured to track a temperature variation of the memory device in real time, perform analog calibration on the bias voltage from the process calibration circuit in real time depending on a result of the tracking, and output the analog-calibrated bias voltage to the write clock buffer.

16. The memory system of claim 15 , wherein the process calibration circuit includes a replica write clock buffer including a bias transistor, and the process calibration circuit is configured to output the one of the plurality of regulated vo

Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Garam
• Kim Yonghun
• Lee Jaewoo
• Kim Kihan
• Chang Hojun

Classifications

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C11/4074

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G11C5/147

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title