Calibration circuit for controlling resistance of output driver circuit, memory device including the same, and operating method of the memory device

Patent metadata

Field	Value
Publication number	US-11145355-B2
Application number	US-202016822164-A
Country	US
Kind code	B2
Filing date	Mar 18, 2020
Priority date	Jul 25, 2019
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

A memory device includes a calibration circuit having a pull-up code generator including a pull-up resistor block and generating a pull-up code, and a pull-down code generator including a replica pull-up resistor block and a pull-down resistor block and generating a pull-down code, and an off chip driver/on die termination circuit providing a termination resistance having a resistance value set by the calibration circuit in a data reception operation and outputting data at an output strength set by the calibration circuit in a data output operation. In a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.

First claim

What is claimed is:

1. A memory device comprising:
a calibration circuit having a pull-up code generator comprising a pull-up resistor block and configured to generate a pull-up code, and a pull-down code generator comprising a replica pull-up resistor block and a pull-down resistor block and configured to generate a pull-down code; and
an off chip driver (OCD)/on die termination (ODT) circuit configured to provide a termination resistance having a resistance value set by the calibration circuit in a data reception operation and to output data at an output strength set by the calibration circuit in a data output operation,
wherein, in a calibration operation, a resistance value of the replica pull-up resistor block is adjusted to be less than a resistance value of the pull-up resistor block, and the pull-down code has a code value by which a resistance value of the pull-down resistor block corresponds to the resistance value of the replica pull-up resistor block.

2. The memory device of claim 1 , wherein
the pull-up resistor block comprises at least one pull-up resistor set connected to a power source voltage, the replica pull-up resistor block comprises a first pull-up resistor set corresponding to that in the pull-up resistor block and an additional pull-up resistor set, and the first pull-up resistor set and the additional pull-up resistor set are connected to the power source voltage and arranged in parallel to each other, and
in the calibration operation, when the additional pull-up resistor set is enabled, the resistance value of the replica pull-up resistor block is adjusted to be less than the resistance value of the pull-up resistor block.

3. The memory device of claim 2 , wherein
the replica pull-up resistor block comprises a plurality of additional pull-up resistor sets, and
in the calibration operation, as the number of the plurality of additional pull-up resistor sets enabled increases, the resistance value of the pull-down resistor block decreases.

4. The memory device of claim 3 , wherein
the memory device receives control information related to the output strength from a memory controller, and
the number of the plurality of additional pull-up resistor sets enabled is adjusted according to the control information.

5. The memory device of claim 1 , wherein
the OCD/ODT circuit comprises a pull-up circuit and a pull-down circuit, the pull-up circuit comprises a plurality of first switches configured to be switched in response to the pull-up code and a plurality of pull-up resistors arranged in correspondence to the plurality of first switches, and the pull-down circuit comprises a plurality of second switches configured to be switched in response to the pull-down code and a plurality of pull-down resistors arranged in correspondence to the plurality of second switches, and
according to code values of the pull-up code and the pull-down code, the pull-up circuit and the pull-down circuit in the OCD/ODT circuit have different resistance values.

6. The memory device of claim 5 , wherein,
in the data output operation, the resistance value of the pull-down circuit in the OCD/ODT circuit is less than the resistance value of the pull-up circuit in the OCD/ODT circuit.

7. The memory device of claim 5 , wherein,
in the data reception operation, the plurality of second switches are turned off, and the plurality of first switches have a turn-on state corresponding to the code value of the pull-up code, to provide the termination resistance.

8. The memory device of claim 1 , wherein
the pull-up resistor block is connected to an external calibration resistor through a pad, and
the pull-up code generator comprises:
a first comparator configured to perform a comparison operation by connecting a first input end thereof to one node of the pull-up resistor block and connecting a second input end thereof to a calibration reference voltage; and
a first counter configured to generate the pull-up code based on a counting operation on a comparison result from the first comparator.

9. The memory device of claim 8 , wherein the pull-down code generator comprises:
a second comparator configured to perform a comparison operation by connecting a first input end thereof to a node between the replica pull-up resistor block and the pull-down resistor block and connecting a second input end thereof to the calibration reference voltage; and
a second counter configured to generate the pull-down code based on a counting operation on a comparison result from the second comparator.

10. The memory device of claim 1 , wherein
the OCD/ODT circuit comprises a pull-up circuit and a pull-down circuit,
the pull-up code corresponds to a first pull-up code provided to the pull-up circuit in the OCD/ODT circuit in the data reception operation,
the calibration circuit performs first and second calibration operations,
in the first calibration operation, the pull-down code generator generates the pull-down code as a code provided to the pull-down circuit in the OCD/ODT circuit in the data output operation,
in the second calibration operation, the pull-down code generator further generates a second pull-up code provided to the pull-up circuit in the OCD/ODT circuit in the data output operation, and
the first pull-up code and the second pull-up code have different code values.

11. The memory device of claim 10 , wherein
the pull-up resistor block comprises at least one pull-up resistor set connected to a power source voltage, the replica pull-up resistor block comprises a first pull-up resistor set corresponding to that in the pull-up resistor block and an additional pull-up resistor set, and the first pull-up resistor set and the additional pull-up resistor set are connected to the power source voltage and arranged in parallel to each other, and
in the first calibration operation, the additional pull-up resistor set is enabled, and in the second calibration operation, the additional pull-up resistor set is disabled.

12. The memory device of claim 11 , wherein
the pull-up circuit in the OCD/ODT circuit has a resistance value varying in response to the second pull-up code in the data output operation,
the pull-down circuit in the OCD/ODT circuit has a resistance value varying in response to the pull-down code, and
in the data output operation, the pull-up circuit and the pull-down circuit in the OCD/ODT circuit have substantially the same resistance value.

13. A calibration circuit configured to control an off chip driver (OCD)/on die termination (ODT) circuit, the calibration circuit comprising:
a pull-up resistor block connected to an external calibration resistor through a pad and comprising at least one pull-up resistor set each connected to a power source voltage;
a first code generator configured to generate a pull-up code for controlling a pull-up circuit in the OCD/ODT circuit, based on a comparison operation comparing a voltage of one node of the pull-up resistor block and a calibration reference voltage;
a replica pull-up resistor block comprising a plurality of pull-up resistor sets connected to the power source voltage;
a pull-down resistor block comprising a pull-down resistor set connected to a ground voltage; and
a second code generator configured to generate a pull-down code for controlling a pull-down circuit in the OCD/ODT circuit, based on a comparison operation comparing a voltage of a node between the replica pull-up resistor block and the pull-down resistor block and the calibration reference voltage,
wherein, in a calibration operation, when a number of enabled pull-up resistor sets in the pull-up resistor block differs from

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hwapyong
• Choi Hundae
• Lee Junha

Classifications

• G11C29/022

  in I/O circuitry · CPC title

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/1066

  Output synchronization · CPC title

• G11C7/1051

  Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits · CPC title

• G11C11/4085 Primary

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title