Continuous time linear equalization including a low frequency equalization circuit which maintains DC gain

Patent metadata

Field	Value
Publication number	US-11201767-B1
Application number	US-202117330937-A
Country	US
Kind code	B1
Filing date	May 26, 2021
Priority date	May 26, 2021
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

Embodiments are directed to continuous time linear equalization including a low frequency equalization circuit which maintains DC gain. A first all-pass filter is coupled to an integrated filter, the integrated filter having a low-pass filter and a second all-pass filter. A high-pass filter is coupled to the first all-pass filter and the integrated filter, a differential input terminal being coupled to the first all-pass filter, the integrated filter, and the high-pass filter, where a differential output terminal is coupled to the high-pass filter.

First claim

What is claimed is:

1. A method comprising:
coupling a first all-pass filter to an integrated filter, the integrated filter comprising a low-pass filter and a second all-pass filter; and
coupling a high-pass filter to the first all-pass filter and the integrated filter, the first all-pass filter, the integrated filter, and the high-pass filter being coupled to a differential input terminal, wherein a differential output terminal is coupled to the high-pass filter.

2. The method of claim 1 , wherein the first all-pass filter comprises a first current source and a second current source respectively coupled to a first transistor and a second transistor.

3. The method of claim 1 , wherein the first all-pass filter and the integrated filter are coupled at a first node and a second node, the high-pass filter being coupled to the first node and the second node.

4. The method of claim 1 , wherein the integrated filter comprises a first current source and a second current source respectively coupled to a first transistor and a second transistor.

5. The method of claim 4 , wherein the integrated filter comprises: a first set of transistors in which one of the first set of transistors is coupled to the first transistor and another one is coupled to the first all-pass filter, and a second set of transistors in which one of the second set of transistors is coupled to the second transistor and another one is coupled to the first all-pass filter.

6. The method of claim 1 , wherein the first all-pass filter and the integrated filter are configured to cause an increase in a magnitude of a low frequency band at the differential output terminal.

7. The method of claim 1 , wherein the first all-pass filter and the integrated filter each have resistors such that a parallel change in values of the resistors affects a magnitude of a low frequency band at the differential output terminal, the magnitude being shifted in accordance with the parallel change in values of the resistors.

8. The method of claim 1 , wherein the integrated filter comprises a low-pass filter curve which is configured to have a frequency shift based on a control signal.

9. The method of claim 1 , wherein the integrated filter comprises a low-pass filter curve which is configured to have a magnitude shift based on a control signal.

10. The method of claim 1 , wherein the first all-pass filter comprises an all-pass filter curve which is configured to have a magnitude shift based on a control signal.

11. A circuit comprising:
a first all-pass filter coupled to an integrated filter, the integrated filter comprising a low-pass filter and a second all-pass filter; and
a high-pass filter coupled to the first all-pass filter and the integrated filter, the first all-pass filter, the integrated filter, and the high-pass filter being coupled to a differential input terminal, wherein a differential output terminal is coupled to the high-pass filter.

12. The circuit of claim 11 , wherein the first all-pass filter comprises a first current source and a second current source respectively coupled to a first transistor and a second transistor.

13. The circuit of claim 11 , wherein the first all-pass filter and the integrated filter are coupled at a first node and a second node, the high-pass filter being coupled to the first node and the second node.

14. The circuit of claim 11 , wherein the integrated filter comprises a first current source and a second current source respectively coupled to a first transistor and a second transistor.

15. The circuit of claim 14 , wherein the integrated filter comprises: a first set of transistors in which one of the first set of transistors is coupled to the first transistor and another one is coupled to the first all-pass filter, and a second set of transistors in which one of the second set of transistors is coupled to the second transistor and another one is coupled to the first all-pass filter.

16. The circuit of claim 11 , wherein the first all-pass filter and the integrated filter are configured to cause an increase in a magnitude of a low frequency band at the differential output terminal.

17. The circuit of claim 11 , wherein the first all-pass filter and the integrated filter each have resistors such that a parallel change in values of the resistors affects a magnitude of a low frequency band at the differential output terminal, the magnitude being shifted in accordance with the parallel change in values of the resistors.

18. The circuit of claim 11 , wherein the integrated filter comprises a low-pass filter curve which is configured to have a frequency shift based on a control signal.

19. The circuit of claim 11 , wherein the integrated filter comprises a low-pass filter curve which is configured to have a magnitude shift based on a control signal.

20. A method comprising:
configuring a first integrated filter circuit comprising a low-pass filter coupled to a first all-pass filter; and
configuring a second integrated filter circuit comprising a high-pass filter coupled to a second all-pass filter, the first integrated filter circuit being coupled to the second integrated filter circuit, the first integrated filter circuit and the second integrated filter circuit being coupled to a differential input terminal, wherein a differential output terminal is coupled to the second integrated filter circuit.

Assignees

• IBM

Inventors

• English Erik
• Marquart Chad Andrew
• Francese Pier Andrea

Classifications

• H03H11/1213

  using transistor amplifiers (H03H11/1204 takes precedence; parallel-T filters H03H11/1295) · CPC title

• H04L25/03878 Primary

  Line equalisers; line build-out devices · CPC title

• H04L25/03127

  using only passive components (H04L25/03121 takes precedence) · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title