Compact four-terminal TCOIL

Patent metadata

Field	Value
Publication number	US-10944397-B1
Application number	US-202016779400-A
Country	US
Kind code	B1
Filing date	Jan 31, 2020
Priority date	Jan 31, 2020
Publication date	Mar 9, 2021
Grant date	Mar 9, 2021

Abstract

The present embodiments relate generally to data communications, and more particularly to systems including high-speed serializer-deserializer circuits having TCOILs. One or more embodiments are directed to a four-terminal TCOIL structure that consumes the same amount of area on a chip as a traditional three-terminal structure, while providing more bandwidth and less reflection and group delay variation.

First claim

What is claimed is:

1. A TCOIL circuit comprising:
a first terminal coupled to an input;
a second terminal coupled to an electrostatic discharge (ESD) device;
a third terminal coupled to a load; and
a fourth terminal coupled to a termination resistor, wherein the first terminal, the second terminal, the third terminal and the fourth terminal of the TCOIL circuit each comprise physically separate metal structures in a plurality of different layers of an integrated circuit.

2. The TCOIL circuit of claim 1 , further comprising:
a first inductor coupled between the first terminal and a center tap;
a second inductor coupled between the center tap and the third terminal; and
a third inductor coupled between the center tap and the fourth terminal.

3. The TCOIL circuit of claim 2 , wherein the third inductor has a smaller inductance than inductances of the first and second inductors.

4. The TCOIL circuit of claim 2 , wherein the third inductor is more electromagnetically coupled to the second inductor than the first inductor.

5. The TCOIL circuit of claim 2 , wherein an amount of electromagnetic coupling between the third inductor and the second inductor is greater than an amount of electromagnetic coupling between the first inductor and the second inductor.

6. The TCOIL circuit of claim 2 , wherein the first, second and third inductors are provided in respective first, second and third different ones of the layers of the integrated circuit.

7. The TCOIL circuit of claim 1 , wherein the first terminal, the second terminal, the third terminal and the fourth terminal of the TCOIL circuit each comprise physically separate electrical terminals of the TCOIL circuit.

8. The TCOIL circuit of claim 1 , where the first terminal is directly connected to the input, the second terminal is directly connected to the ESD device, the third terminal is directly connected to the load, and the fourth terminal is directly connected to the termination resistor.

9. A transceiver comprising:
an input or output termination; and
a TCOIL circuit coupled to one of the input or output termination, the TCOIL circuit including
a first terminal coupled to an input;
a second terminal coupled to an electrostatic discharge (ESD) device;
a third terminal coupled to a load; and
a fourth terminal coupled to a termination resistor, wherein the first terminal, the second terminal, the third terminal and the fourth terminal of the TCOIL circuit each comprise physically separate metal structures in a plurality of different layers of an integrated circuit.

10. The transceiver of claim 9 , wherein the TCOIL circuit further includes:
a first inductor coupled between the first terminal and a center tap;
a second inductor coupled between the center tap and the third terminal; and
a third inductor coupled between the center tap and the fourth terminal.

11. The transceiver of claim 10 , wherein the third inductor has a smaller inductance than inductances of the first and second inductors.

12. The transceiver of claim 10 , wherein the third inductor is more electromagnetically coupled to the second inductor than the first inductor.

13. The transceiver of claim 10 , wherein an amount of electromagnetic coupling between the third inductor and the second inductor is greater than an amount of electromagnetic coupling between the first inductor and the second inductor.

14. The transceiver of claim 10 , wherein the first, second and third inductors are provided in respective first, second and third different ones of the layers of the integrated circuit.

15. A serial-deserializer (SerDes) circuit comprising:
a transceiver, the transceiver having an input or output termination; and
a TCOIL circuit coupled to one of the input or output termination, the TCOIL circuit including
a first terminal coupled to an input;
a second terminal coupled to an electrostatic discharge (ESD) device;
a third terminal coupled to a load; and
a fourth terminal coupled to a termination resistor, wherein the first terminal, the second terminal, the third terminal and the fourth terminal of the TCOIL circuit each comprise physically separate metal structures in a plurality of different layers of an integrated circuit.

16. The SerDes circuit of claim 15 , wherein the TCOIL circuit further includes:
a first inductor coupled between the first terminal and a center tap;
a second inductor coupled between the center tap and the third terminal; and
a third inductor coupled between the center tap and the fourth terminal.

17. The SerDes circuit of claim 16 , wherein the third inductor has a smaller inductance than inductances of the first and second inductors.

18. The SerDes circuit of claim 16 , wherein the third inductor is more electromagnetically coupled to the second inductor than the first inductor.

19. The SerDes circuit of claim 16 , wherein an amount of electromagnetic coupling between the third inductor and the second inductor is greater than an amount of electromagnetic coupling between the first inductor and the second inductor.

20. The SerDes circuit of claim 16 , wherein the first, second and third inductors are provided in respective first, second and third different ones of the layers of the integrated circuit.

Assignees

• Cadence Design Systems Inc

Inventors

• Yuan Xiaobin
• Loizos Dimitri
• Lam Hiu Ming
• Safi-Harab Mouna

Classifications

• H04L25/0298

  Arrangement for terminating transmission lines · CPC title

• H04L25/0266

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title

• H03K19/017545 Primary

  Coupling arrangements; Impedance matching circuits · CPC title

• H03K17/6872 Primary

  using complementary field-effect transistors · CPC title

• H04L25/0272

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title