Methods for programming a memory device, memory devices, and memory systems

Patent metadata

Field	Value
Publication number	US-12387794-B2
Application number	US-202218090402-A
Country	US
Kind code	B2
Filing date	Dec 28, 2022
Priority date	Aug 31, 2021
Publication date	Aug 12, 2025
Grant date	Aug 12, 2025

Abstract

A method for programming a memory device, a memory device, and a memory system are disclosed. The memory device includes planes. The method includes: programming the planes by using a programming voltage incremented with a first step size; verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using an other programming voltage incremented with a second step size less than the first step size.

First claim

What is claimed is:

1. A method for programming a memory device comprising planes, the method comprising:
programming the planes by using a first programming voltage incremented with a first step size;
verifying the planes, and in response to determining that one or more planes are with a verification exception, disabling the one or more planes with the verification exception; and
in response to the one or more planes with the verification exception being disabled, programming remaining one or more planes that are not disabled by using a second programming voltage incremented with a second step size;
wherein the second step size is determined according to a number of the one or more disabled planes and less than the first step size.

2. The method according to claim 1 , wherein:
the second step size is a second value when the number of the one or more disabled planes is a first value;
the second step size is a fourth value when the number of the one or more disabled planes is a third value; and
the third value is greater than the first value, and correspondingly, the fourth value is less than the second value.

3. The method according to claim 1 , wherein each plane comprises a plurality of memory cells arranged in rows and columns, and programming the planes by using the first programming voltage incremented with the first step size comprises:
programming a plurality of selected memory cells in the planes by using the first programming voltage incremented with the first step size.

4. The method according to claim 3 , further comprising:
applying a first pass voltage incremented with a third step size to a plurality of unselected memory cells in the planes, when programming the planes by using the first programming voltage incremented with the first step size.

5. The method according to claim 4 , further comprising:
applying a second pass voltage incremented with a fourth step size to unselected memory cells in the one or more planes that is not disabled, when programming the one or more planes that is not disabled by using the second programming voltage incremented with the second step size,
wherein the fourth step size is less than the third step size.

6. The method according to claim 1 , wherein:
the first step size is in a range of about 0.15 volt to about 0.5 volt; and
the second step size is in a range of about 0.1 volt to about 0.45 volt.

7. The method according to claim 1 , wherein verifying the planes comprises:
verifying whether each plane reaches a predetermined programming state; and
in response to one plane being verified for a predetermined number of times without reaching the predetermined programming state, determining that the one plane is with the verification exception.

8. The method according to claim 1 , further comprising:
terminating programming of the planes, when all planes are disabled.

9. A memory device, comprising:
a memory array comprising planes;
a row driver configured to apply voltages to the planes; and
a control logic circuit configured to:
control the row driver to apply a first programming voltage incremented with a first step size to program the planes,
verify the planes, and in response to determining that the one or more planes are with a verification exception, disable the one or more planes with the verification exception, and
in response to the one or more planes being disabled, control the row driver to apply a second programming voltage incremented with a second step size to further program remaining one or more planes that are not disabled,
wherein the second step size is determined according to a number of the one or more disabled planes and less than the first step size.

10. The memory device of claim 9 , wherein:
the second step size is a second value when the number of the one or more disabled planes is a first value;
the second step size is a fourth value when the number of the one or more disabled planes is a third value; and
the third value is greater than the first value, and correspondingly, the fourth value is less than the second value.

11. The memory device of claim 9 , wherein each plane comprises memory a plurality of cells arranged in rows and columns, and the control logic circuit is further configured to:
control the row driver to apply the first programming voltage incremented with the first step size to selected memory cells in the planes.

12. The memory device according to claim 11 , wherein the control logic circuit is further configured to:
control the row driver to apply a first pass voltage incremented with a third step size to unselected memory cells in the planes, when applying the first programming voltage incremented with the first step size to selected memory cells in the planes.

13. The memory device according to claim 12 , wherein the control logic circuit is further configured to
control the row driver to apply a second pass voltage incremented with a fourth step size to unselected memory cells in the one or more planes that are not disabled, and apply the second programming voltage incremented with the second step size to selected memory cells in the one or more planes that are not disabled,
wherein the fourth step size is less than the third step size.

14. The memory device according to claim 9 , wherein:
the first step size is in a range of about 0.15 volt to about 1 volt; and
the second step size is in a range of about 0.1 volt to about 0.45 volt.

15. The memory device according to claim 9 , wherein the control logic circuit is further configured to:
verify whether each plane reaches a predetermined programming state; and
in response to one plane being verified for a predetermined number of times without reaching the predetermined programming state, determine that the one plane is with the verification exception.

16. The memory device according to claim 9 , wherein the control logic circuit is further configured to:
terminate programming of the planes, when all planes are disabled.

17. A memory system, comprising:
one or more memory devices; and
a memory controller coupled to the memory devices;
wherein each of the memory devices comprises:
a memory array comprising planes;
a row driver configured to apply voltages to the planes; and
a control logic circuit configured to:
control the row driver to apply a first programming voltage incremented with a first step size to program the planes,
verify the planes, and in response to determining that the one or more planes are with a verification exception, disable the one or more planes with the verification exception, and
in response to the one or more planes being disabled, control the row driver to apply a second programming voltage incremented with a second step size to further program remaining one or more planes that are not disabled,
wherein the second step size is determined according to a number of the one or more disabled planes and less than the first step size.

18. The memory system of claim 17 , wherein:
the second step size is a second value when the number of the one or more disabled planes is a first value,
the second step size is a fourth value when the number of the one or more disabled planes is a third value;
wherein the third value is greater than the first value, and correspondingly, the fourth value is less than the second value.

19. The memory system of claim 17 , wherein each plane comprises memory a plurality of cells arranged in rows and columns, and the control logic circuit is further configured to:
c

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Jiang Ke
• Mei Xiaodong
• Guo Xiaojiang

Classifications

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3436

  Arrangements for verifying correct programming or erasure · CPC title

• G11C16/12 Primary

  Programming voltage switching circuits · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title