Semiconductor storage device

Patent metadata

Field	Value
Publication number	US-11398277-B2
Application number	US-202117200308-A
Country	US
Kind code	B2
Filing date	Mar 12, 2021
Priority date	Sep 15, 2020
Publication date	Jul 26, 2022
Grant date	Jul 26, 2022

Abstract

A semiconductor storage device of an embodiment includes a control circuit configured to execute a writing sequence in which a loop including a program operation that writes data to memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing a program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence, and the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

First claim

What is claimed is:

1. A semiconductor storage device comprising:
a memory cell array including a plurality of memory cells;
a plurality of word lines connected with respective gates of the plurality of memory cells;
a word line driver configured to apply a program voltage to the word lines at writing of data to the plurality of memory cells;
a plurality of bit lines each connected with one end of a corresponding one of the plurality of memory cells;
a bit line driver configured to apply a bit line voltage to the plurality of bit lines and detect data in the plurality of memory cells through the plurality of bit lines; and
a control circuit configured to control the word line driver and the bit line driver to execute a writing sequence in which a loop including a program operation that writes data to the memory cells and a program verify operation that verifies the data written in the memory cells is repeated a plurality of times by increasing the program voltage by a predetermined step-up voltage each time, the control circuit being capable of executing reading verify that verifies the data written in the memory cells in the writing sequence,
wherein the control circuit detects characteristic variation of a characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

2. The semiconductor storage device according to claim 1 , wherein the control circuit detects the characteristic variation of the characteristic that causes disturbance at the writing, and determines whether to perform the reading verify based on a result of the detection.

3. The semiconductor storage device according to claim 2 , wherein the control circuit detects, as the characteristic variation of the characteristic that causes disturbance, variation of the number of loops of the program operation and the program verify operation.

4. The semiconductor storage device according to claim 3 , wherein the control circuit determines whether to perform the reading verify based on whether the variation of the number of loops exceeds a reference value at factory shipment.

5. The semiconductor storage device according to claim 4 , wherein the control circuit controls the program voltage for each of a plurality of groups of the word lines in the writing sequence and determines whether to perform the reading verify by comparing the variation of the number of loops with a reference set for each group at factory shipment.

6. The semiconductor storage device according to claim 3 , wherein the control circuit calculates the number of loops per page in the writing sequence and determines whether to perform the reading verify by comparing variation of the number of loops per page with a reference value.

7. The semiconductor storage device according to claim 6 , wherein the control circuit controls the program voltage for each of a plurality of groups of the word lines in the writing sequence and determines whether to perform the reading verify by comparing the variation of the number of loops per page with a reference value set for each group.

8. The semiconductor storage device according to claim 3 , wherein the control circuit calculates the number of loops per word line in the writing sequence and determines whether to perform the reading verify by comparing variation of the number of loops per word line with a reference value.

9. The semiconductor storage device according to claim 3 , wherein
the memory cell array, the plurality of word lines, the word line driver, the plurality of bit lines, and the bit line driver are each provided in plurality in a multi-plane configuration, and
the control circuit determines whether to perform the reading verify based on comparison between the number of loops for one plane and the number of loops for another plane in the multi-plane configuration.

10. The semiconductor storage device according to claim 3 , wherein when data of a plurality of levels corresponding to data of three or more values is written to the memory cells, the control circuit determines whether to perform the reading verify based on the number of loops at writing completion of a predetermined level.

11. The semiconductor storage device according to claim 2 , wherein the control circuit determines whether to perform the reading verify by comparing, with a reference set for each group at factory shipment, variation of the number of failed cells for the program verify operation after a predetermined number of loops is reached in the writing sequence.

12. The semiconductor storage device according to claim 2 , wherein
the memory cell array, the plurality of word lines, the word line driver, the plurality of bit lines, and the bit line driver are each provided in plurality in a multi-plane configuration, and
when failure of data writing to the memory cells occurs at one plane in the multi-plane configuration, the control circuit performs the reading verify at another plane.

13. The semiconductor storage device according to claim 1 , wherein at erasure in which an erasure loop including an erasure operation that erases data written in the memory cells and an erase verify that verifies erasure of the data is repeated, the control circuit detects the characteristic variation of the characteristic that causes disturbance, and determines whether to perform the reading verify based on a result of the detection.

14. The semiconductor storage device according to claim 13 , wherein the control circuit detects variation of the number of erasure loops as the characteristic variation of the characteristic that causes disturbance.

15. The semiconductor storage device according to claim 14 , wherein the control circuit determines whether to perform the reading verify based on whether the variation of the number of erasure loops exceeds a reference value at factory shipment.

16. The semiconductor storage device according to claim 14 , wherein the control circuit determines whether to perform the reading verify by comparing the variation of the number of erasure loops for erasure at an identical block in the memory cell array with a reference value.

17. The semiconductor storage device according to claim 14 , wherein the control circuit determines whether to perform the reading verify by comparing, with a reference value, a difference in the number of erasure loops between continuous erasure operations at different blocks of the memory cell array.

18. The semiconductor storage device according to claim 14 , wherein
the memory cell array, the plurality of word lines, the word line driver, the plurality of bit lines, and the bit line driver are each provided in plurality in a multi-plane configuration, and
the control circuit determines whether to perform the reading verify based on comparison between the number of erasure loops at one plane in the multi-plane configuration and the number of erasure loops at another plane.

19. The semiconductor storage device according to claim 14 , wherein the control circuit determines whether to perform the reading verify by comparing variation of the number of failed cells in the erase verify with a reference at factory shipment.

20. The semiconductor storage device according to claim 14 , wherein
the memory cell array, the plurality of word lines, the word line driver, the plurality of bit lines, and the bit line driver are each provided in plurality in a multi-plane configuration, and
the control circuit determines whether to perform the reading verify based on compa

Assignees

• Kioxia Corp

Inventors

• Kusaka Takuya
• Arizono Daisuke
• Harada Yoshikazu

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/3459 Primary

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title