Identifying failure type in NVM programmed in SLC mode using a single programming pulse with no verification

Patent metadata

Field	Value
Publication number	US-11348643-B2
Application number	US-202016799874-A
Country	US
Kind code	B2
Filing date	Feb 25, 2020
Priority date	Feb 25, 2020
Publication date	May 31, 2022
Grant date	May 31, 2022

Abstract

A controller includes an interface and storage circuitry. The interface is configured to communicate with a memory device that includes multiple memory cells organized in memory blocks. The memory device supporting programming of the memory cells with enabled or disabled program-verification. The storage circuitry is configured to disable the program-verification, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse, to read the data from the group of the memory cells. In response to detecting a failure in reading the data, the storage circuitry is configured to distinguish between whether the memory cells in the group belong to a defective memory block or were under-programmed, and when identifying that the memory cells in the group were under-programmed, to perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.

First claim

The invention claimed is:

1. A controller, comprising:
an interface configured to communicate with a memory device comprising multiple memory cells organized in memory blocks, the memory device supporting programming of the memory cells with enabled or disabled program-verification operation that, when enabled, verifies that selected memory cells being programmed have reached respective predefined thresholds; and
a processor configured to:
disable the program-verification operation and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse;
after concluding programming of the data using the single programming pulse with the program-verification operation disabled, read the data from the group of the memory cells;
in response to detecting a failure in reading the data, distinguish between (i) whether the memory cells in the group belong to a defective memory block and (ii) whether the memory cells in the group were under-programmed by the single programming pulse; and
when identifying that the memory cells in the group were under-programmed, perform a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.

2. The controller according to claim 1 , wherein the processor is configured to check a number of bit-flip occurrences in the read data, to identify that the memory cells were under-programmed when the number of the bit-flip occurrences exceeds a first predefined number, and to identify that the memory cells in the group belong to a defective memory block when the number of the bit-flip occurrences exceeds a second predefined number larger than the first predefined number.

3. The controller according to claim 1 , wherein the processor is configured to count in the read data a first number of one-valued bits and a second number of zero-valued bits, and to identify that the memory cells in the group belong to a defective memory block when a balance measure between the first number and the second number exceeds a predefined balance threshold.

4. The controller according to claim 1 , wherein the processor is configured to estimate a threshold-voltage distribution by reading the memory cells in the group using multiple read thresholds, and to identify that the memory cells in the group were under-programmed when identifying two distinct peaks in the estimated threshold-voltage distribution.

5. The controller according to claim 1 , wherein the processor is configured to identify pages that failed reading in a same memory block, and to identify that the memory cells in the group were under-programmed when a number of the failing pages in the same memory block is below a predefined number.

6. The controller according to claim 1 , wherein the memory blocks are organized in multiple planes, and wherein the processor is configured to:
program the data across the multiple planes in parallel;

read the data from the group of memory cells in the multiple planes; and
identify that part of the memory cells in the group belong to a defective memory block in a respective plane, when reading the data fails only in the respective plane among the multiple planes.

7. The controller according to claim 1 , wherein the processor is configured to read from the memory cells in the group multiple code words that were encoded before storage in accordance with an Error Correction Code (ECC), and to identify that the memory cells in the group belong to a defective memory block when detecting that all of the multiple code words are undecodable or having a number of errors exceeding a predefined threshold number.

8. The controller according to claim 1 , wherein the processor is configured to perform the corrective action by enabling the program-verification operation in subsequent program operations to the memory cells in the group.

9. The controller according to claim 1 , wherein the processor is configured to perform the corrective action by increasing an amplitude of the single programming pulse in subsequent program operations to the memory cells in the group.

10. The controller according to claim 1 , wherein in response to identifying that the memory cells in the group were under-programmed, the processor is configured to estimate a severity level of under-programming applied to the memory cells in the group, and to select the corrective action from among multiple predefined corrective action tasks, based on the severity of the under-programming.

11. The controller according to claim 1 , wherein the processor is configured to estimate a failure rate in reading data from the group of the memory cells, and upon detecting that the failure rate exceeds a predefined rate, to enable the program-verification operation in subsequent program operations to the memory cells in the group.

12. The controller according to claim 1 , wherein the memory cells in the group belong to a stripe comprising multiple memory blocks in multiple respective planes, wherein the processor is configured to:
read the memory cells in the group across the multiple memory blocks of the stripe; and
upon detecting a failure in reading the memory cells in a given memory block, assign the given memory block to a stripe in which the memory cells are programmed with the program-verification operation enabled.

13. A method for data storage, comprising:
in a controller that communicates with a memory device comprising multiple memory cells organized in memory blocks, the memory device supports programming the memory cells with enabled or disabled program-verification operation that, when enabled, verifies that selected memory cells being programmed have reached respective predefined thresholds,
disabling the program-verification operation, and program data to a group of the memory cells in a Single Level Cell (SLC) mode using a single programming pulse;
after concluding programming of the data using the single programming pulse with the program-verification operation disabled, reading the data from the group of the memory cells;
in response to detecting a failure in reading the data, distinguishing (i) whether the memory cells in the group belong to a defective memory block and (ii) the memory cells in the group were under-programmed by the single programming pulse; and
when identifying that the memory cells in the group were under-programmed, performing a corrective action to prevent under-programming in subsequent program operations to the memory cells in the group.

14. The method according to claim 13 , and comprising checking a number of bit-flip occurrences in the read data, identifying that the memory cells were under-programmed when the number of the bit-flip occurrences exceeds a first predefined number, and identifying that the memory cells in the group belong to a defective memory block when the number of the bit-flip occurrences exceeds a second predefined number larger than the first predefined number.

15. The method according to claim 13 , and comprising counting in the read data a first number of one-valued bits and a second number of zero-valued bits, and identifying that the memory cells in the group belong to a defective memory block when a balance measure between the first number and the second number exceeds a predefined balance threshold.

16. The method according to claim 13 , and comprising estimating a threshold-voltage distribution by reading the memory cells in the group using multiple read thresholds, and identifying that the memory cells in the group were under-programmed when identifying two distinct peaks in the e

Assignees

• Apple Inc

Inventors

• Sagron Itay
• Shappir Assaf

Classifications

• G06F2201/81

  Threshold · CPC title

• G11C16/10 Primary

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title