Sram with hierarchical bit lines in monolithic 3d integrated chips

Patent metadata

Field	Value
Publication number	US-2019273084-A1
Application number	US-201616349242-A
Country	US
Kind code	A1
Filing date	Dec 29, 2016
Priority date	Dec 29, 2016
Publication date	Sep 5, 2019
Grant date	—

Abstract

A memory device includes a first plurality of memory cells, a second plurality of memory cells, and a local sense amplifier between the first plurality of memory cells and the second plurality of memory cells, all on a first level, and a local bit line on a second level. The second level is vertically separated by one or more first inter-level dielectric layers from the first level in a first direction and the local bit line is electrically coupled to each memory cell of the first plurality of memory cells and the second plurality of memory cells, as well as the local sense amplifier. The memory device also includes a global bit line on a third level vertically separated by one or more inter-level dielectric layers from the first level in a second direction opposite the first direction, with the global bit line electrically coupled to the local sense amplifier.

First claim

1 . A memory device, comprising:
a first plurality of memory cells extending laterally on a first level; a second plurality of memory cells extending laterally on the first level; a local sense amplifier on the first level between the first plurality of memory cells and the second plurality of memory cells; a local bit line extending laterally on a second level, the second level vertically separated by one or more first inter-level dielectric layers from the first level in a first direction, the local bit line electrically coupled to each memory cell of the first plurality of memory cells, each memory cell of the second plurality of memory cells, and the local sense amplifier; and a global bit line extending laterally on a third level vertically separated by one or more second inter-level dielectric layers from the first level in a second direction opposite the first direction, the global bit line electrically coupled to the local sense amplifier.

2 . The memory device of claim 1 , further comprising:
a plurality of local sense amplifiers; a plurality of local bit lines; and a global sense amplifier on the first level electrically coupled to the global bit line.

3 . The memory device of claim 1 , further comprising a first plurality of inter-layer interconnects through the one or more first inter-level dielectric layers to electrically couple the local bit line to each memory cell of the first plurality of memory cells, each memory cell of the second plurality of memory cells, and the local sense amplifier.

4 . The memory device of claim 3 , further comprising a second plurality of inter-layer interconnects through the one or more second inter-level dielectric layers to electrically couple the global bit line to the local sense amplifier.

5 . The memory device of claim 1 , wherein a power supply extends laterally along the third level.

6 . The memory device of claim 1 , wherein the local bit line is wider than the global bit line.

7 . The memory device of claim 1 , wherein the local bit line is a first local bit line and the global bit line is a first global bit line, the memory device further comprising:
a second local bit line extending laterally on the second level, the second local bit line electrically coupled to each memory cell of the first plurality of memory cells, each memory cell of the second plurality of memory cells, and the local sense amplifier; and a second global bit line extending laterally on the third level, the second global bit line electrically coupled to the local sense amplifier.

8 . The memory device of claim 7 , further comprising:
a first plurality of wordlines extending laterally on a fourth level vertically separated by one or more third inter-level dielectric layers from the third level in the second direction, each wordline of the first plurality of wordlines electrically coupled to the first local bit line, the second local bit line, and a memory cell of the first plurality of memory cells; and a second plurality of wordlines extending laterally on the fourth level, each wordline of the second plurality of wordlines electrically coupled to the first local bit line, the second local bit line, and a memory cell of the second plurality of memory cells.

9 . The memory device of claim 8 , further comprising:
a third plurality of inter-layer interconnects through the one or more first inter-level dielectric layers, the one or more second inter-level dielectric layers, and the one or more third inter-level dielectric layers to electrically couple each wordline to the local sense amplifier; and a fourth plurality of inter-layer interconnects through the one or more second inter-level dielectric layers and the one or more third inter-level dielectric layers to electrically couple each wordline to one memory cell of either the first plurality of memory cells or the second plurality of memory cells.

10 . The memory device of claim 9 , wherein the memory device is a static random access memory cell.

11 . A method of fabricating a memory device, comprising:
disposing a first plurality of memory cells extending laterally on a first level on a substrate; disposing a second plurality of memory cells extending laterally on the first level on the substrate; disposing a local sense amplifier on the first level on the substrate; removing at least a portion of the substrate; disposing one or more first inter-level dielectric layers below the first level; disposing a local bit line extending laterally on a second level below the one or more first inter-level dielectric layers; etching a first plurality of inter-layer interconnects through the one or more inter-level dielectric layers between the first level and the second level to electrically couple the local bit line to each memory cell of the first plurality of memory cells each memory cell of the second plurality of memory cells, and the local sense amplifier; disposing one or more second inter-level dielectric layers over the first level; disposing a global bit line extending laterally on a third level over the one or more second inter-level dielectric layers; and etching a second plurality of inter-layer interconnects through the one or more second inter-level dielectric layers between the first level and the third level to electrically couple the global bit line to the local sense amplifier.

12 . The method of claim 11 , further comprising disposing a global sense amplifier on the first level, wherein the second plurality of inter-layer interconnects includes an inter-layer interconnect to electrically couple the global sense amplifier to the global bit line.

13 . The method of claim 11 , further comprising disposing a power supply on the third level.

14 . The method of claim 11 , wherein the local bit line is wider than the global bit line.

15 . The method according to claim 11 , wherein the local bit line is a first local bit line and the global bit line is a first global bit line, the method further comprising:
disposing a second local bit line on the second level, wherein the first plurality of inter-layer interconnects includes inter-layer interconnects to electrically couple the second local bit line to each memory cell of the first plurality of memory cells, each memory cell of the second plurality of memory cells, and the local sense amplifier; and disposing a second global bit line on the third level, wherein the second plurality of inter-layer interconnects includes an inter-layer interconnect to electrically couple the second global bit line to the local sense amplifier.

16 . The method of claim 15 , further comprising:
disposing one or more third inter-level dielectric layers over the second level; disposing a first plurality of wordlines extending laterally on a fourth level over the one or more third inter-level dielectric layers; disposing a second plurality of wordlines extending laterally on the fourth level; etching a third plurality of inter-layer interconnects through the one or more third inter-level dielectric layers and the one or more second inter-level dielectric layers, the third plurality of inter-layer interconnects including inter-layer interconnects to electrically couple each wordline of the first plurality of wordlines to a memory cell of the first plurality of memory cells and including inter-layer interconnects to electrically couple each wordline of the second plurality of wordlines to a memory cell of the second plurality of memory cells; and etching a fourth plurality of inter-layer interconnects through the one or more third inter-level d

Assignees

• Intel Corp

Inventors

• Wang Yih

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title