Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods

Patent metadata

Field	Value
Publication number	US-12381174-B2
Application number	US-202217809675-A
Country	US
Kind code	B2
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

Integrated circuit (IC) packages employing wire bond channel over package substrate, and related fabrication methods. The IC package includes a first semiconductor die (“first die”) and a first electronic device each coupled to a package substrate. To provide signal routing paths between the first die and the first electronic device, the IC package includes a wire bond channel that includes wire bonds coupled between first and second metal pads coupled to the respective first die and first electronic device to provide signal routing paths between the first die and first electronic device. The wire bonds extend outside of the package substrate in a vertical direction. The wire bond channel may be able to support more direct signal routing paths between the first die and the first electronic device without having to route such signal routing paths around a KoZ in the package substrate.

First claim

What is claimed is:

1. An integrated circuit (IC) package, comprising:
a package substrate comprising a first surface extending in a first direction;
a first die coupled to the first surface of the package substrate; and
a wire bond channel, comprising:
one or more first metal pads coupled to the first surface of the package substrate and coupled to the first die;
one or more second metal pads coupled to the first surface of the package substrate; and
one or more wire bonds disposed outside the package substrate, the one or more wire bonds each coupling a respective first metal pad of the one or more first metal pads to a respective second metal pad of the one or more second metal pads.

2. The IC package of claim 1 , wherein the one or more wire bonds extend over the first surface of the package substrate in a second direction orthogonal to the first direction.

3. The IC package of claim 1 , further comprising a second electronic device coupled to the first surface of the package substrate, the second electronic device adjacent to the first die;
wherein at least a portion of at least one of the one or more wire bonds intersect a first vertical plane intersecting the second electronic device.

4. The IC package of claim 3 , wherein at least a portion of each of the one or more wire bonds intersects a vertical plane intersecting the second electronic device.

5. The IC package of claim 3 , wherein:
the second electronic device comprises a first side adjacent to the first die;
the one or more first metal pads are disposed adjacent to the first die and between the first die and the first side of the second electronic device in the first direction; and
the one or more second metal pads are disposed adjacent to a second side of the second electronic device.

6. The IC package of claim 3 , wherein:
the package substrate further comprises an outer metallization layer adjacent to the first surface of the package substrate;
the second electronic device is coupled to the outer metallization layer; and
the outer metallization layer comprises a keep out zone (KoZ) region comprising or more first metal lines, wherein the KoZ region extends in the first direction and at least partially intersects a first plane orthogonal to the first direction.

7. The IC package of claim 3 , wherein the second electronic device comprises a second die.

8. The IC package of claim 3 , wherein the second electronic device comprises a deep trench capacitor.

9. The IC package of claim 1 , wherein:
the package substrate further comprises:
an outer metallization layer adjacent to the first surface of the package substrate, the outer metallization layer comprises:
a keep out zone (KoZ) region, the KoZ region comprising one or more first metal lines extending in the first direction; and

at least a portion of at least one wire bond of the one or more wire bonds intersects a first vertical plane orthogonal to the first direction and intersecting at least a portion of the KoZ region.

10. The IC package of claim 9 , wherein the IC package does not comprise a second electronic device coupled to the first surface of the package substrate that intersects the first vertical plane.

11. The IC package of claim 9 , wherein:
the outer metallization layer comprises one or more second metal lines coupled to the one or more first metal pads; and
the first die is coupled to the one or more second metal lines.

12. The IC package of claim 11 , wherein:
the one or more second metal lines extend in a third direction towards the one or more first metal pads; and
the one or more wire bonds extend in a fourth direction different from the third direction from the one or more first metal pads towards the one or more second metal pads.

13. The IC package of claim 1 , wherein:
the one or more first metal pads are exposed from the first surface of the package substrate; and
the one or more second metal pads are exposed from the first surface of the package substrate.

14. The IC package of claim 1 , wherein:
the package substrate comprises a metallization layer comprising a plurality of metal lines;
the one or more first metal pads are each coupled to a respective one of the plurality of metal lines; and
the first die is coupled to the plurality of metal lines.

15. A method of fabricating an integrated circuit (IC) package, comprising:
providing a package substrate comprising a first surface extending in a first direction;
coupling a first die to the first surface of the package substrate; and
forming a wire bond channel, comprising:
forming one or more first metal pads coupled the first surface of the package substrate and coupled to the first die;
forming one or more second metal pads coupled to the first surface of the package substrate;
coupling a first end of each of one or more wire bonds outside the package substrate to the one or more first metal pads outside the package substrate; and
coupling a second end of each of the one or more wire bonds outside the package substrate to the one or more second metal pads.

16. The method of claim 15 , further comprising extending the one or more wire bonds over the first surface of the package substrate in a second direction orthogonal to the first direction.

17. The method of claim 15 , further comprising:
coupling a second electronic device to the first surface of the package substrate and adjacent to the first die; and
extending the one or more wire bonds intersecting a first vertical plane intersecting the second electronic device.

18. The method of claim 17 , wherein:
the coupling the second electronic device to the first surface of the package substrate further comprises coupling a first side of the second electronic device adjacent to the first die;
the forming the one or more first metal pads further comprises forming the one or more first metal pads adjacent to the first die and between the first die and the first side of the second electronic device in the first direction; and
the forming the one or more second metal pads further comprises forming the one or more second metal pads adjacent to a second side of the second electronic device.

19. The method of claim 17 , wherein:
the package substrate further comprises an outer metallization layer adjacent to the first surface of the package substrate, the outer metallization layer comprises a keep out zone (KoZ) region comprising one or more first metal lines, the KoZ region extending in the first direction; and
the coupling the second electronic device to the first surface of the package substrate further comprises coupling the second electronic device to the outer metallization layer such that the second electronic device at least partially intersects the first vertical plane.

20. The method of claim 15 , wherein:
the package substrate further comprises an outer metallization layer adjacent to the first surface of the package substrate, the outer metallization layer comprises a keep out zone (KoZ) region comprising one or more first metal lines extending in the first direction; and
the method further comprising:
extending the one or more wire bonds intersecting a first vertical plane orthogonal to the first direction and intersecting at least a portion of the KoZ region.

21. The method of claim 20 , further comprising not coupling a second electronic device to the first surface of the package substrate that intersects the first vertical plane.

22. The method of claim

Assignees

• Qualcomm Inc

Inventors

• Patil Aniket
• We Hong Bok
• Buot Joan Rey Villarba

Classifications

• H10W72/07554

  changes in dispositions · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title