Seal for microelectronic assembly

US12381119B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12381119-B2
Application numberUS-202318463080-A
CountryUS
Kind codeB2
Filing dateSep 7, 2023
Priority dateMar 21, 2017
Publication dateAug 5, 2025
Grant dateAug 5, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

First claim

Opening claim text (preview).

What is claimed is: 1. A bonded structure, comprising: a first microelectronic component comprising a first surface and a second surface opposite the first surface, wherein the first surface comprises a first dielectric and a first conductive feature; a second microelectronic component comprising a third surface comprising a second dielectric and a second conductive feature, wherein the first surface is in contact with the third surface to form a bond joint, and wherein the bond joint comprises a dielectric-to-dielectric direct bond between the first dielectric and the second dielectric and a metal-to-metal direct bond between the first conductive feature and the second conductive feature; and a channel extending continuously around an interior region of the bonded structure, wherein a height of the channel extends at least across the bond joint, the channel having sidewalls at least partially covered with metal, the sidewalls extending from the second surface into the first microelectronic component. 2. The bonded structure of claim 1 , wherein the metal conformally coats at least portions of the sidewalls. 3. The bonded structure of claim 2 , wherein the channel comprises a floor between the sidewalls, the floor conformally coated by the metal. 4. The bonded structure of claim 1 , wherein the bonded structure comprises a sensor. 5. The bonded structure of claim 1 , wherein the channel extends through the first microelectronic component and across the bond joint. 6. The bonded structure of claim 5 , wherein the channel extends partially into the second microelectronic component. 7. The bonded structure of claim 1 , wherein the second microelectronic component comprises a cavity. 8. A bonded structure, comprising: a first microelectronic component having a first surface comprising a first dielectric and a first conductive feature and a second surface opposite the first surface; a second microelectronic component having a third surface comprising a second dielectric and a second conductive feature; a bond joint between the first surface and the third surface, wherein the first dielectric is directly bonded to the second dielectric, and wherein the first conductive feature is directly bonded to the second conductive feature; and a channel extending at least partially around an interior region of the bonded structure, the channel extending from the second surface through the first microelectronic component and across the bond joint into at least a portion of the second microelectronic component, a metallic material disposed in the channel. 9. The bonded structure of claim 8 , wherein the metallic material is disposed conformally along a sidewall of the channel. 10. The bonded structure of claim 8 , wherein the metallic material partially fills the channel. 11. The bonded structure of claim 8 , wherein the channel extends continuously around the interior region of the bonded structure. 12. The bonded structure of claim 8 , wherein the channel extends partially into the second microelectronic component. 13. The bonded structure of claim 8 , wherein the bond joint comprises directly bonded insulating materials. 14. The bonded structure of claim 13 , wherein the bond joint further comprises directly bonded metal interconnects at the bond joint. 15. The bonded structure of claim 8 , wherein the channel is annularly continuous around a periphery of the bond joint. 16. A bonded structure, comprising: a first microelectronic component comprising a first surface, a second surface opposite the first surface, and a side edge extending from the first surface to the second surface; a second microelectronic component comprising a third surface directly bonded to the first surface without an intervening adhesive to form a bond joint; and a channel extending continuously around an interior region of the bonded structure, the channel having sidewalls extending from the second surface into the first microelectronic component, wherein, the bond joint comprises directly bonded insulating materials and directly bonded metal interconnects, and wherein, between the side edge and the interior region as viewed in a side cross-section of the bonded structure, metal is present at every elevation between the bond joint and the second surface. 17. The bonded structure of claim 16 , wherein the metal conformally coats at least portions of the sidewalls of the channel. 18. The bonded structure of claim 16 , wherein the channel extends through the first microelectronic component and across the bond joint into at least a portion of the second microelectronic component. 19. A microelectronic assembly, comprising: a first microelectronic component having a first surface comprising a first dielectric and a first conductive feature; a second microelectronic component having a second surface comprising a second dielectric and a second conductive feature; a bond joint between the first surface and the second surface, wherein the first dielectric is directly bonded to the second dielectric, and wherein the first conductive feature is directly bonded to the second conductive feature; and a channel comprising an annular shape, wherein the channel extends around a periphery of the first microelectronic component, and wherein the channel extends at least to the bond joint. 20. The microelectronic assembly of claim 19 , wherein the channel comprises a metallic material that seals the bond joint between the first microelectronic component and the second microelectronic component. 21. The microelectronic assembly of claim 19 , wherein a metallic material is disposed in the channel. 22. The microelectronic assembly of claim 21 , wherein the channel comprises a hermetic seal to prevent fluid leakage at the bond joint greater than 1×10 −6 atm-cm 3 per second. 23. The microelectronic assembly of claim 19 , wherein the channel comprises a layer of a metallic material disposed over a sidewall surface of the channel. 24. The microelectronic assembly of claim 19 , further comprising a third microelectronic component coupled to the second microelectronic component such that the second microelectronic component is positioned between the first microelectronic component and the third microelectronic component.

Assignees

Inventors

Classifications

  • Containers comprising an insulating or insulated base · CPC title

  • characterised by their shape · CPC title

  • Containers or parts thereof · CPC title

  • H10W76/60Primary

    Seals · CPC title

  • Bonding of solid lids or wafers to the substrate · CPC title

Patent family

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Frequently asked questions

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What does patent US12381119B2 cover?
Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periph…
Who is the assignee on this patent?
Adeia Semiconductor Bonding Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10W76/60. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 05 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).