Asynchronous full-adder with majority or minority gates to generate sum false output

Patent metadata

Field	Value
Publication number	US-12379898-B1
Application number	US-202217650226-A
Country	US
Kind code	B1
Filing date	Feb 7, 2022
Priority date	Feb 7, 2022
Publication date	Aug 5, 2025
Grant date	Aug 5, 2025

Abstract

Asynchronous full-adder circuit is described. The full-adder includes majority and/or minority gates some of which receive two first inputs (A.t, A.f), two second inputs (B.t, B.f), two carry inputs (Cin.t, Cin.f), third acknowledgement input (Cout.e), and fourth acknowledgement input (Sum.e), and generate controls to control gates of transistors, wherein the transistors are coupled to generate two carry outputs (Cout.t, Cout.e), two sum outputs (Sum.t, Sum.e), first acknowledgement output (A.e), second acknowledgement output (B.e), and third acknowledgement output (Cin.e). The majority and/or minority gates comprise CMOS gates or multi-input capacitive circuitries. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the asynchronous full-adder circuit. Asynchronous full-adders coupled in series is used to implement a carry-ripple adder.

First claim

We claim:

1. An apparatus comprising:
a first data channel comprising two first inputs and a first acknowledgement output;
a second data channel comprising two second inputs and a second acknowledgement output;
a third data channel comprising two carry inputs and a third acknowledgement output;
a fourth data channel comprising two carry outputs and a third acknowledgement input;
a fifth data channel comprising two sum outputs and a fourth acknowledgement input; and
a full-adder coupled to the first data channel, the second data channel, the third data channel, the fourth data channel, and the fifth data channel, wherein the full-adder comprises majority and/or minority gates some of which receive the two first inputs, the two second inputs, the two carry inputs, the third acknowledgement input, and the fourth acknowledgement input, and generate controls to control gates of transistors, wherein the transistors are coupled to generate the two carry outputs, the two sum outputs, the first acknowledgement output, the second acknowledgement output, and the third acknowledgement output, and wherein the full-adder comprises a circuitry to generate a sum false output of the two sum outputs.

2. The apparatus of claim 1 , wherein the circuitry comprises:
a p-type transistor coupled to a supply rail;
a first n-type transistor coupled in series with the p-type transistor; and
a 3-input minority gate having an output coupled to gate terminals of the p-type transistor and the first n-type transistor.

3. The apparatus of claim 2 , wherein the 3-input minority gate includes:
a first input to receive the fourth acknowledgement input;
a second input to receive an enable signal; and
a third input coupled to the output of the 3-input minority gate.

4. The apparatus of claim 2 , wherein the circuitry comprises:
a second n-type transistor coupled in series with the first n-type transistor, and to a ground supply rail; and
a first 5-input majority gate having an output that couples to a gate terminal of the second n-type transistor.

5. The apparatus of claim 4 , wherein the first 5-input majority gate includes:
a first input to receive a first false carry input of the two carry inputs;
a second input to receive a first false input of the two first inputs;
a third input to receive a first false input of the two second inputs;
a fourth input coupled to the ground supply rail; and
a fifth input coupled to the ground supply rail.

6. The apparatus of claim 2 , wherein the circuitry comprises:
a third n-type transistor coupled in series with the first n-type transistor, and to a ground supply rail; and
a second 5-input majority gate having an output that couples to a gate terminal of the third n-type transistor.

7. The apparatus of claim 6 , wherein the second 5-input majority gate includes:
a first input to receive a first false carry input of the two carry inputs;
a second input to receive a first true input of the two first inputs;
a third input to receive a first true input of the two second inputs;
a fourth input coupled to the ground supply rail; and
a fifth input coupled to the ground supply rail.

8. The apparatus of claim 2 , wherein the circuitry comprises:
a fourth n-type transistor coupled in series with the first n-type transistor, and to a ground supply rail; and
a third 5-input majority gate having an output that couples to a gate terminal of the fourth n-type transistor.

9. The apparatus of claim 8 , wherein the third 5-input majority gate includes:
a first input to receive a first true carry input of the two carry inputs;
a second input to receive a first false input of the two first inputs;
a third input to receive a first true input of the two second inputs;
a fourth input coupled to the ground supply rail; and
a fifth input coupled to the ground supply rail.

10. The apparatus of claim 2 , wherein the circuitry comprises:
a fifth n-type transistor coupled in series with the first n-type transistor, and to a ground supply rail; and
a fourth 5-input majority gate having an output that couples to a gate terminal of the fifth n-type transistor.

11. The apparatus of claim 10 , wherein the fourth 5-input majority gate includes:
a first input to receive a first true carry input of the two carry inputs;
a second input to receive a first true input of the two first inputs;
a third input to receive a first false input of the two second inputs;
a fourth input coupled to the ground supply rail; and
a fifth input coupled to the ground supply rail.

12. The apparatus of claim 1 , wherein the majority and/or minority gates are implemented as CMOS gates, MESO gates, or quantum cellular automata.

13. The apparatus of claim 1 , wherein the majority and/or minority gates are implemented capacitive-input circuits.

14. The apparatus of claim 2 , wherein the circuitry comprises an inverter coupled to the p-type transistor and the first n-type transistor, and wherein an output of the inverter is the sum false output.

Assignees

• Kepler Computing Inc

Inventors

• Imam Nabil
• Mathuriya Amrita
• Odinaka Ikenna
• Rios Rafael
• Dokania Rajeev Kumar
• Manipatruni Sasikanth

Classifications

• G06F7/503

  using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal · CPC title

• H03K19/23

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• G06F7/508 Primary

  using carry look-ahead circuits · CPC title