Chip tracking with marking database
US-10108925-B1 · Oct 23, 2018 · US
US12379666B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12379666-B2 |
| Application number | US-202318137131-A |
| Country | US |
| Kind code | B2 |
| Filing date | Apr 20, 2023 |
| Priority date | Apr 29, 2022 |
| Publication date | Aug 5, 2025 |
| Grant date | Aug 5, 2025 |
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A method of generating chip-specific identification code marks on semiconductor chips includes patterning a resist layer over a semiconductor wafer by laser direct image exposure, the patterning including writing chip-specific identification codes into the resist layer over chip areas of the semiconductor wafer. The patterned resist layer is then developed.
Opening claim text (preview).
What is claimed is: 1. A method of generating chip-specific identification code marks on semiconductor chips, the method comprising: patterning a resist layer over a semiconductor wafer by laser direct image exposure, wherein the patterning includes writing chip-specific identification codes into the resist layer over chip areas of the semiconductor wafer and defining a chip pad layout in the resist layer over the chip areas, wherein the resist layer is an uppermost resist layer and remains permanently on the semiconductor wafer; and developing the patterned resist layer, wherein the chip-specific identification code marks are formed and the chip pads are exposed in the developed resist layer. 2. The method of claim 1 , wherein the resist layer is of a negative tone resist. 3. The method of claim 1 , wherein the resist layer is of a positive tone resist. 4. The method of claim 1 , wherein the patterning has a minimum patterning width of equal to or greater than 1 μm. 5. The method of claim 1 , wherein a laser beam energy applied for the laser direct image exposure is insufficient for laser ablation in semiconductor technology. 6. The method of claim 1 , wherein the chip-specific identification code marks are optically visible on the chip. 7. The method of claim 1 , wherein the chip areas are power chip areas or MEMS chip areas. 8. The method of claim 1 , wherein the chip areas are CMOS logic chip areas. 9. The method of claim 1 , wherein the chip-specific identification codes comprise a cryptographic key for authenticating the semiconductor chips.
characterised by the processes involved to create the masks · CPC title
using lasers · CPC title
using masks for insulating materials · CPC title
Formed on wafers or substrates before dicing and remaining on chips after dicing · CPC title
digital information, e.g. bar codes · CPC title
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