Method of producing hybrid semiconductor wafer

Patent metadata

Field	Value
Publication number	US-12374675-B2
Application number	US-202218055763-A
Country	US
Kind code	B2
Filing date	Nov 15, 2022
Priority date	Nov 16, 2021
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed. The method results in a hybrid wafer comprising a planar top layer formed of the material of the continuous layer with one or more islands embedded therein, the top layer of the islands being formed by the top layer of the active material portion of the one or more tiles.

First claim

What is claimed is:

1. A method of producing a hybrid wafer configured to be processed for producing one or more semiconductor components, the method comprising:
producing one or more tiles, each of the one or more tiles comprising a carrier portion and an active material portion on the carrier portion such that a back side of the carrier portion forms a back side of each of the one or more tiles and the active material portion is located at a front side of each of the one or more tiles;
producing an assembly, the assembly comprising:
a temporary carrier wafer, and
the one or more tiles, wherein the one or more tiles are removably attached face down to the temporary carrier wafer, such that the back sides of the one or more tiles are facing away from the temporary carrier wafer;

bonding the assembly to a permanent carrier wafer by bonding the back sides of the one or more tiles to the permanent carrier wafer,
wherein a continuous layer surrounds the one or more tiles,
wherein the continuous layer is either part of the assembly or is formed after bonding the assembly to the permanent carrier wafer, and
wherein the continuous layer is formed of a material that is different from at least a top layer of the active material portion; and
removing the temporary carrier wafer, thereby obtaining the hybrid wafer, the hybrid wafer comprising the permanent carrier wafer having bonded thereto a planar top layer formed of the material of the continuous layer with one or more islands embedded therein, the top layer of the one or more islands being formed by the top layer of the active material portion of the one or more tiles.

2. The method according to claim 1 wherein:
the assembly comprises the continuous layer surrounding each of the one or more tiles, wherein the continuous layer is also removably attached to the temporary carrier wafer, so that the back side of the continuous layer is facing away from the temporary carrier wafer,
the method further comprising:
planarizing the assembly, so that the back sides of the one or more tiles and of the continuous layer are rendered essentially co-planar, and
bonding the assembly to the permanent carrier wafer by bonding the co-planar back sides of the one or more tiles and of the continuous layer to the permanent carrier wafer.

3. The method according to claim 2 , wherein the continuous layer is formed by a pocket wafer, and wherein producing the assembly further comprises:
producing the pocket wafer, the pocket wafer comprising one or more cavities through a complete thickness of the pocket wafer, a shape of the one or more cavities corresponding respectively to a shape of the one or more tiles so that the one or more tiles can be placed respectively inside the one or more cavities,
removably attaching the pocket wafer to the temporary carrier wafer, and
placing the one or more tiles face down inside the respective one or more cavities.

4. The method according to claim 3 , further comprising filling gaps remaining between the one or more tiles and sidewalls of the respective cavities after the one or more tiles have been placed inside the cavities.

5. The method according to claim 4 , wherein the one or more tiles further comprise a protective layer on the active material portion, and wherein filling the gaps takes place after bonding the assembly to the permanent carrier wafer and comprises:
depositing a gap fill material in the gaps and on top of the one or more tiles, and wherein the method includes planarizing the gap fill material and removing the protective layer.

6. The method according to claim 3 , wherein the pocket wafer is a semiconductor wafer, and wherein the active material portion of the one or more tiles comprises at least a top layer of a III-V semiconductor material.

7. The method according to claim 3 , wherein the pocket wafer and the permanent carrier wafer are semiconductor wafers having a diameter of 200 mm or 300 mm.

8. The method according to claim 3 , wherein a first capping layer is formed on the one or more tiles and on the pocket wafer, after placing the one or more tiles in the cavities, and before planarizing the assembly.

9. The method according to claim 3 , wherein a dielectric capping and/or bonding layer is formed on the one or more tiles and on the pocket wafer, after planarizing the assembly.

10. The method according to claim 3 , wherein the temporary carrier wafer is provided with a temporary adhesive layer, wherein the one or more tiles are removably attached to the temporary adhesive layer, and wherein the method further includes removing the temporary adhesive layer.

11. The method according to claim 2 , wherein producing the assembly comprises:
producing one or more alignment markers on the temporary carrier wafer,
producing a temporary adhesive layer on the temporary carrier wafer,
attaching the one or more tiles to the temporary adhesive layer, using the one or more alignment markers for positioning the one or more tiles, thereby removably attaching the one or more tiles to the carrier wafer, and
depositing a layer of the material on the temporary adhesive layer in an area surrounding each of the one or more tiles and on top of the one or more tiles, wherein the layer forms the continuous layer surrounding each of the one or more tiles,
and wherein the method includes removing the temporary adhesive layer.

12. The method according to claim 1 , wherein the one or more tiles further comprise a protective layer on the active material portion, wherein the continuous layer is not part of the assembly, and wherein producing the assembly comprises:
producing one or more alignment markers on the temporary carrier wafer, and
removably attaching the one or more tiles to the temporary carrier wafer using the one or more alignment markers for positioning the one or more tiles,
wherein the method further comprises:
bonding the back sides of the one or more tiles to the permanent carrier wafer,
removing the temporary carrier wafer,
depositing a layer of the material in an area surrounding each of the one or more tiles and on top of the one or more tiles, wherein the layer forms the continuous layer surrounding each of the one or more tiles, and
planarizing the continuous layer and removing the protective layer from the active material portion of the one or more tiles, thereby obtaining the hybrid wafer.

13. The method according to claim 1 , wherein the active material portion of the one or more tiles comprises one or more layers that have been processed and/or patterned prior to producing the one or more tiles.

14. A method for producing at least one semiconductor component, the method comprising:
providing the hybrid wafer produced according to the method of claim 1 ,
processing the hybrid wafer to thereby produce a semiconductor component on an area comprising a portion of the continuous layer and the one or more of islands, and
separating the semiconductor component from the rest of the hybrid wafer.

15. The method of claim 1 , wherein the active material portion comprises a semiconductor material suitable for processing active semiconductor devices thereon.

16. The method of claim 1 , wherein the active material portion comprises a second material suitable for patterning of the material.

17. The method of claim 1 , wherein the active material portion is a pristine layer that has not been processed or patterned.

18. The method of claim 1 , wherein the active material portion comprises the top layer, wherein the top layer is a pristine layer.

Assignees

• Imec Vzw

Inventors

• Karve Gauri
• Li Yunlong
• Haspeslagh Luc
• Soussan Philippe
• Sabuncuoglu Tezcan Deniz

Classifications

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/014

  using batch processing · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/07331

  Connecting techniques · CPC title

• H10W72/07307

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title