Embedded gallium-nitride in silicon

Patent metadata

Field	Value
Publication number	US-9911602-B2
Application number	US-201615232860-A
Country	US
Kind code	B2
Filing date	Aug 10, 2016
Priority date	Mar 11, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A method and structure for integrating gallium nitride into a semiconductor substrate. The method may also include means for isolating the gallium nitride from the semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a substrate, wherein a trench is located in the substrate, and the substrate comprises silicon, and wherein a horizontal surface of the trench is silicon;
a gallium-nitride layer filling the trench, wherein a top surface of the gallium-nitride layer is coplanar with a top surface of the substrate, wherein the bottom surface of the gallium-nitride layer is in direct contact with the horizontal surface of the trench;
a semiconductor structure located on the substrate;
a GaN structure located above the gallium nitride layer; and
a dielectric layer located along a vertical surface of the trench and between the gallium-nitride layer and the substrate.

2. The structure of claim 1 , wherein the substrate further comprises a semiconductor on insulator structure.

3. The structure of claim 1 , wherein the semiconductor structure comprises a fuse, EDRAM, SRAM, or a gate.

4. The structure of claim 1 , wherein the GaN structure comprises an LED.

5. The structure of claim 1 , wherein the gallium-nitride layer comprises 30 to 70 mole % gallium and 30 to 70 mole % nitrogen.

6. A semiconductor structure comprising:
a substrate, wherein a trench is located in the substrate, and the substrate comprises silicon, and wherein a horizontal surface of the trench is silicon;
a gallium-nitride layer located in the trench;
an aluminum-gallium-nitride layer is located on the gallium nitride layer, wherein the aluminum-gallium-nitride layer and gallium-nitride layer fill the trench, wherein a top surface of the aluminum-gallium-nitride layer is coplanar with a top surface of the substrate, and wherein the bottom surface of the gallium-nitride layer is in direct contact with the horizontal surface of the trench;
a semiconductor structure located on the substrate;
a GaN structure located above the gallium-nitride layer.

7. The structure of claim 6 , wherein the substrate further comprises a semiconductor on insulator structure.

8. The structure of claim 6 , wherein the semiconductor structure comprises a fuse, EDRAM, SRAM, or a gate.

9. The structure of claim 6 , wherein the GaN structure comprises an LED.

10. The structure of claim 6 further comprising a dielectric layer located along a vertical surface of the trench and between the gallium-nitride layer and the substrate.

Assignees

• IBM

Inventors

• Gallagher William J
• Leobandung Effendi
• Sadana Devendra K
• Shahidi Ghavam G

Classifications

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10P90/00

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title

• H10P76/405

  characterised by their composition, e.g. multilayer masks · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/282

  of inorganic materials · CPC title