Heterogeneous integration of 3D SI and III-V vertical nanowire structures for mixed signal circuits fabrication

Patent metadata

Field	Value
Publication number	US-10319642-B2
Application number	US-201715667305-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Jul 8, 2016
Publication date	Jun 11, 2019
Grant date	Jun 11, 2019

Abstract

A method of forming Si or Ge-based and III-V based vertically integrated nanowires on a single substrate and the resulting device are provided. Embodiments include forming first trenches in a Si, Ge, III-V, or Si x Ge 1-x substrate; forming a conformal SiN, SiO x C y N z layer over side and bottom surfaces of the first trenches; filling the first trenches with SiO x ; forming a first mask over portions of the Si, Ge, III-V, or Si x Ge 1-x substrate; removing exposed portions of the Si, Ge, III-V, or Si x Ge 1-x substrate, forming second trenches; forming III-V, III-V x M y , or Si nanowires in the second trenches; removing the first mask and forming a second mask over the III-V, III-V x M y , or Si nanowires and intervening first trenches; removing the SiO x layer, forming third trenches; and removing the second mask.

First claim

What is claimed is:

1. A method comprising:
forming a substrate stack including an amorphous silicon (a-Si) followed by n or p doping or doped polysilicon (poly-Si) layer and a silicon oxycarbide (SiOC) layer;
forming first and second groups of trenches in the substrate stack down to the doped a-Si/poly-Si layer of the substrate stack;
forming a first mask over the second group of trenches;
forming silicon (Si), germanium (Ge) or silicon germanium (Si x Ge 1-x ) nanowires in the first group of trenches;
removing the first mask and forming a second mask over the Si, Ge, or Si x Ge 1-x nanowires;
forming III-V nanowires in the second group of trenches;
removing the second mask; and
planarizing the Si, Ge, or Si x Ge 1-x and III-V nanowires down to the SiOC layer.

2. The method according to claim 1 , comprising forming the substrate stack by:
forming a Si substrate;
forming a buffer oxide layer over the Si substrate;
forming the a-Si or doped poly-Si layer over the oxide layer;
forming a first silicon nitride (SiN) layer over the a-Si or doped poly-Si layer;
forming the SiOC layer over the first SiN layer; and
forming a second SiN layer over the SiOC layer.

3. The method according to claim 1 , comprising forming the trenches within the substrate stack by:
self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), direct surface assembly (nanoimprint), or extreme ultraviolet (EUV) lithography.

4. The method according to claim 1 , comprising forming the Si, Ge, or Si x Ge 1-x nanowires by:
depositing a nickel (Ni) or gold (Au) nanoparticle in each of the first group of trenches by self-assembly in sol-gel or by metal organic chemical vapor deposition (MOCVD) or atomic layer growth (ALD); and
growing the Si, Ge, or Si x Ge 1-x nanowires to a desired height.

5. The method according to claim 4 , comprising pre-cleaning the first group of trenches prior to depositing the Ni or Au nanoparticle.

6. The method according to claim 1 , comprising forming the III-V nanowires by:
depositing an aluminum (Al), Ni, or gallium (Ga) nanoparticle in each of the second group of trenches by self-assembly in sol-gel or by MOCVD, ALD;
growing the III-V nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth or chemical vapor deposition (CVD) growth with in-situ doping during growth; and
removing the second mask prior to planarizing the Si, Ge, or Si x Ge 1-x and III-V nanowires.

7. The method according to claim 6 , comprising pre-cleaning the second group of trenches prior to depositing the Al, Ni, or Ga nanoparticle.

8. The method according to claim 6 , comprising planarizing the Si, Ge, or Si x Ge 1-x and III-V nanowires by chemical mechanical planarization (CMP).

9. The method according to claim 1 , comprising forming the III-V nanowires of a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs).

10. The method according to claim 1 , wherein the metal catalyst comprises Ni, Al, Au, silver (Ag), titanium (Ti), erbium (Er), platinum (Pt), palladium (Pd), indium (In), Tin (Sn), antimony (Sb), Zirconium (Zr), vanadium (V), hafnium (Hf), tungsten (W), cobalt (Co), tantalum (Ta), lanthanum (La), ruthenium (Ru), molybdenum (Mo), Ga, or iron (Fe).

11. A method comprising:
forming a substrate stack including an amorphous silicon (a-Si) followed by n or p doping or doped polysilicon (poly-Si) layer and a silicon oxycarbide (SiOC) layer;
forming first and second groups of trenches by self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), direct surface assembly (nanoimprint), or extreme ultraviolet (EUV) lithography in the substrate stack down to the doped a-Si/poly-Si layer of the substrate stack;
forming a first mask over the second group of trenches;
forming silicon (Si), germanium (Ge) or silicon germanium (Si x Ge 1-x ) nanowires in the first group of trenches by VLS or chemical vapor deposition (CVD) process with in-situ doping;
removing the first mask and forming a second mask over the Si, Ge, or Si x Ge 1-x nanowires;
forming III-V nanowires of a combination of indium phosphide (InP), indium arsenide (InAs), gallium nitride (GaN), or gallium arsenide (GaAs) in the second group of trenches by a metal catalyst VLS or CVD growth with in-situ doping;
removing the second mask; and
planarizing the Si, Ge, or Si x Ge 1-x and III-V nanowires down to the SiOC layer by chemical mechanical planarization (CMP).

12. The method according to claim 11 , comprising forming the substrate stack by:
forming a Si substrate;
forming a buffer oxide layer over the Si substrate;
forming the a-Si or doped poly-Si layer over the oxide layer;
forming a first silicon nitride (SiN) layer over the a-Si or doped poly-Si layer;
forming the SiOC layer over the first SiN layer; and
forming a second SiN layer over the SiOC layer.

13. The method according to claim 11 , comprising forming the Si, Ge, or Si x Ge 1-x nanowires by:
pre-cleaning the first group of trenches;
depositing a nickel (Ni) or gold (Au) nanoparticle in each of the first group of trenches by self-assembly in sol-gel or by metal organic chemical vapor deposition (MOCVD) or atomic layer growth (ALD); and
growing the Si, Ge, or Si x Ge 1-x nanowires to a desired height.

14. The method according to claim 11 , comprising forming the III-V nanowires by:
pre-cleaning the second group of trenches;
depositing an aluminum (Al), Ni, or gallium (Ga) nanoparticle in each of the second group of trenches by self-assembly in sol-gel or by MOCVD, ALD;
growing the III-V nanowires to a desired height by a metal catalyst vertical vapor liquid solid (VLS) growth or chemical vapor deposition (CVD) growth with in-situ doping during growth; and
removing the second mask prior to planarizing the Si, Ge, or Si x Ge 1-x and III-V nanowires.

Assignees

• Globalfoundries Inc

Inventors

• PATIL Suraj Kumar
• Jacob Ajey P

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2925

  Surface structures · CPC title