Machine learning-based scatterometry and feed forward techniques for gate-all-around transistors

Patent metadata

Field	Value
Publication number	US-12374570-B2
Application number	US-202217901676-A
Country	US
Kind code	B2
Filing date	Sep 1, 2022
Priority date	Sep 1, 2022
Publication date	Jul 29, 2025
Grant date	Jul 29, 2025

Abstract

This disclosure describes systems, methods, and devices for estimating dimple etch recess depth in a gate-all-around transistor. A method may include receiving, by a device, first measurements of the gate-all-around transistor, the first measurements based on first optical data from a spacer etch stage of fabricating the gate-all-around transistor; inputting, by the at least one processor, using a feed forward network, the first measurements to a machine learning model trained to estimate dimple etch recess in the gate-all-around transistor; inputting, by the at least one processor, to the machine learning model, second optical data from a dimple etch stage of fabricating the gate-all-around transistor; and generating, by the at least one processor, using the machine learning model, based on the second optical data and the first measurements, second measurements comprising the first measurements and dimple etch recess estimates for the gate-all-around transistor.

First claim

What is claimed is:

1. A method for estimating dimple etch recess depth in a gate-all-around transistor, the method comprising:
receiving, by at least one processor of a device, first measurements of the gate-all-around transistor, the first measurements based on first optical data from a spacer etch stage of fabricating the gate-all-around transistor;
inputting, by the at least one processor, using a feed forward network, the first measurements to a machine learning model trained to estimate dimple etch recesses in the gate-all-around transistor;
inputting, by the at least one processor, to the machine learning model, second optical data from a dimple etch stage of fabricating the gate-all-around transistor; and
generating, by the at least one processor, using the machine learning model, based on the second optical data and the first measurements, second measurements comprising the first measurements and individual dimple etch recess estimates for the gate-all-around transistor;
performing a dimple etch fabrication portion of a fabrication process using the individual dimple etch recess estimates.

2. The method of claim 1 , further comprising:
refraining from identifying, using the machine learning model, a correlation between the second optical data and the first measurements.

3. The method of claim 1 , wherein the dimple etch recess estimates comprise a first estimate of a first dimple recess depth, a second estimate of a second dimple recess depth, and an average of the first estimate and the second estimate.

4. The method of claim 1 , wherein the machine learning model is trained using training data indicative of transmission electron microscope data associated with dimple etch recesses of the gate-all-around transistor.

5. The method of claim 1 , wherein the machine learning model is trained using training data indicative of a single set of process skews comprising percentages of Silicon Germanium associated with atomic layer depositions of the gate-all-around transistor.

6. The method of claim 1 , wherein the first measurements comprise a polysilicon measurement, and wherein the dimple etch recess estimates are associated with Silicon Germanium.

7. The method of claim 1 , wherein generating the second measurements comprises estimating the dimple etch recess estimates based on atomic layer deposition measurements of the first measurements.

8. The method of claim 1 , wherein generating the second measurements comprises including the first measurements in the second measurements without modifying or re-measuring the first measurements.

9. A non-transitory computer-readable storage medium comprising instructions to cause processing circuitry of a device for estimating dimple etch recess depth in a gate-all-around transistor, upon execution of the instructions by the processing circuitry, to:
receive first measurements of the gate-all-around transistor, the first measurements based on first optical data from a spacer etch stage of fabricating the gate-all-around transistor;
input, using a feed forward network, the first measurements to a machine learning model trained to estimate dimple etch recesses in the gate-all-around transistor;
input, to the machine learning model, second optical data from a dimple etch stage of fabricating the gate-all-around transistor; and
generate, using the machine learning model, based on the second optical data and the first measurements, second measurements comprising the first measurements and individual dimple etch recess estimates for the gate-all-around transistor;
perform a dimple etch fabrication portion of a fabrication process using the individual dimple etch recess estimates.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions further cause the processing circuitry to:
refrain from identifying, using the machine learning model, a correlation between the second optical data and the first measurements.

11. The non-transitory computer-readable storage medium of claim 9 , wherein the dimple etch recess estimates comprise a first estimate of a first dimple recess depth, a second estimate of a second dimple recess depth, and an average of the first estimate and the second estimate.

12. The non-transitory computer-readable storage medium of claim 9 , wherein the machine learning model is trained using training data indicative of transmission electron microscope data associated with dimple etch recesses of the gate-all-around transistor.

13. The non-transitory computer-readable storage medium of claim 9 , wherein the machine learning model is trained using training data indicative of a single set of process skews comprising percentages of Silicon Germanium associated with atomic layer depositions of the gate-all-around transistor.

14. The non-transitory computer-readable storage medium of claim 9 , wherein the first measurements comprise a polysilicon measurement, and wherein the dimple etch recess estimates are associated with Silicon Germanium.

15. The non-transitory computer-readable storage medium of claim 9 , wherein to generate the second measurements comprises to estimate the dimple etch recess estimates based on atomic layer deposition measurements of the first measurements.

16. The non-transitory computer-readable storage medium of claim 9 , wherein to generate the second measurements comprises to include the first measurements in the second measurements without modifying or re-measuring the first measurements.

17. A device for estimating dimple etch recess depth in a gate-all-around transistor, the device comprising processing circuitry coupled to memory, the processing circuitry being configured to:
receive first measurements of the gate-all-around transistor, the first measurements based on first optical data from a spacer etch stage of fabricating the gate-all-around transistor;
input, using a feed forward network, the first measurements to a machine learning model trained to estimate dimple etch recesses in the gate-all-around transistor;
input, to the machine learning model, second optical data from a dimple etch stage of fabricating the gate-all-around transistor; and
generate, using the machine learning model, based on the second optical data and the first measurements, second measurements comprising the first measurements and individual dimple etch recess estimates for the gate-all-around transistor;
perform a dimple etch fabrication portion of a fabrication process using the individual dimple etch recess estimates.

18. The device of claim 17 , wherein the processing circuitry is further configured to:
refrain from identifying, using the machine learning model, a correlation between the second optical data and the first measurements.

19. The device of claim 17 , wherein the dimple etch recess estimates comprise a first estimate of a first dimple recess depth, a second estimate of a second dimple recess depth, and an average of the first estimate and the second estimate.

20. The device of claim 17 , wherein the machine learning model is trained using training data indicative of transmission electron microscope data associated with dimple etch recesses of the gate-all-around transistor.

Assignees

• Intel Corp

Inventors

• Verma Deepak
• Agarwal Navnit
• Das Ayan

Classifications

• H10P72/0604 Primary

  Process monitoring, e.g. flow or thickness monitoring · CPC title

• G06F18/214

  Generating training patterns; Bootstrap methods, e.g. bagging or boosting · CPC title

• G06N20/00

  Machine learning · CPC title

• G06N3/08

  Learning methods · CPC title

• G06N3/0499

  Feedforward networks · CPC title