Integration methods to fabricate internal spacers for nanowire devices

Patent metadata

Field	Value
Publication number	US-9859368-B2
Application number	US-201615333123-A
Country	US
Kind code	B2
Filing date	Oct 24, 2016
Priority date	Jun 29, 2012
Publication date	Jan 2, 2018
Grant date	Jan 2, 2018

Abstract

A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

First claim

What is claimed is:

1. A method, comprising:
providing a substrate having:
a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires separated by sacrificial material;
a gate structure defining a channel region of the device, wherein the gate structure has a pair of gate sidewalls; and
a pair of source/drain regions on opposite sides of the channel region;

removing the gate structure, exposing the surfaces of the nanowire stack;
removing the sacrificial material from between the nanowires to expose the nanowire surfaces within the channel region;
removing a portion of sacrificial material between the nanowires in the source/drain region, creating a dimple in the source/drain region; and
filling the dimples with spacer material to form a plurality of internal spacers.

2. The method of claim 1 , wherein the substrate is an SOI substrate having a base substrate, an insulation layer, and a single-crystal layer, wherein a bottom-most nanowire in the nanowire stack is formed from the single-crystal layer, and wherein the method further comprises etching to remove a portion of the insulation layer to form a dimple adjacent to the channel region.

3. The method of claim 1 , wherein the dimples are etched in alignment with the external spacers.

4. The method of claim 1 , wherein filling the dimples with spacer material comprises conformally depositing spacer material on the exposed nanowire surfaces.

5. The method of claim 4 , further comprising removing a portion of the spacer material to expose the nanowire surfaces within the channel region.

6. The method of claim 4 , further comprising transforming the spacer material within the channel region, wherein transforming the spacer material comprises altering the etch selectivity of the spacer material.

7. The method of claim 6 , wherein transforming the spacer material comprises one or more of plasma treatment, implantation, or oxidation.

8. The method of claim 1 , further comprising depositing a gate dielectric and gate electrode within the channel region.

9. A method, comprising:
providing a substrate having:
a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires separated by sacrificial material;
a gate structure defining a channel region of the device, wherein the gate structure has a pair of gate sidewalls; and
a pair of source/drain regions on opposite sides of the channel region;

removing the sacrificial material from between the nanowires in the source/drain region;
creating a plurality of dimples adjacent to the channel region; and
filling the dimples with spacer material to form a plurality of internal spacers.

10. The method of claim 9 , wherein the substrate is an SOI substrate having a base substrate, an insulation layer, and a single-crystal layer, wherein a bottom-most nanowire in the nanowire stack is formed from the single-crystal layer, and wherein the method further comprises etching to remove a portion of the insulation layer to form a dimple adjacent to the channel region.

11. The method of claim 9 , wherein the dimples are etched in alignment with the external spacers.

12. The method of claim 9 , wherein filling the dimples with spacer material comprises depositing spacer material in the source/drain region.

13. The method of claim 12 , further comprising removing a portion of the spacer material to expose the nanowire surfaces within the channel region.

14. The method of claim 12 , further comprising transforming a portion of the spacer material within the source/drain region, but external to the dimple, wherein transforming the spacer material comprises altering the etch selectivity of the spacer material.

15. The method of claim 14 , wherein transforming the spacer material comprises one or more of plasma treatment, implantation, or oxidation.

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Kuhn Kelin J
• Ghani Tahir
• Murthy Anand S
• Armstrong Mark
• Rios Rafael
• Pethe Abhijit Jayant
• Rachmady Willy

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/40

  into insulating materials · CPC title

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• H01L29/0847

  Electricity · mapped topic